Through Silicon Via (TSV) to Transistor Noise Coupling Characterization, M.Sc. Thesis Sharif University of Technology ; Sarvari, Reza (Supervisor)
Abstract
Due to the physical limitations of the conventional 2D ICs at Giga-Scale Integration, modern technologies have been emerged. Among them, through silicon via (TSV) - based 3D ICs have been used to continue Moore’s law in the interconnect era. In these systems, dies are stacked at z-direction after wafer thinning. Electrical connections between stacked dies are done by TSVs. One important advantage of 3D integration technology is their ability to stack heterogeneous systems with different technologies on a single chip. This will not only increase interconnect density but also will reduce the delay and power consumption. However, nowadays, fabrication and optimum design of TSVs are still big...
Cataloging briefThrough Silicon Via (TSV) to Transistor Noise Coupling Characterization, M.Sc. Thesis Sharif University of Technology ; Sarvari, Reza (Supervisor)
Abstract
Due to the physical limitations of the conventional 2D ICs at Giga-Scale Integration, modern technologies have been emerged. Among them, through silicon via (TSV) - based 3D ICs have been used to continue Moore’s law in the interconnect era. In these systems, dies are stacked at z-direction after wafer thinning. Electrical connections between stacked dies are done by TSVs. One important advantage of 3D integration technology is their ability to stack heterogeneous systems with different technologies on a single chip. This will not only increase interconnect density but also will reduce the delay and power consumption. However, nowadays, fabrication and optimum design of TSVs are still big...
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