Processor Allocation for Future Multi-Core Chip-Multiprocessor, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. For decades, this approach provides desired performance for parallel and multithreaded workloads. On the other hand, rising of utilization wall limits the number of transistors that can be powered on in chip and result in a large region to be dark. So, same as before trend for performance scaling in future multi processor, an appropriate architecture is essential. There are some structures for this era which used specialization approach to cope with the limited power budget. Therefore, in this thesis, we propose a general-purpose platform that provides...
Cataloging briefProcessor Allocation for Future Multi-Core Chip-Multiprocessor, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. For decades, this approach provides desired performance for parallel and multithreaded workloads. On the other hand, rising of utilization wall limits the number of transistors that can be powered on in chip and result in a large region to be dark. So, same as before trend for performance scaling in future multi processor, an appropriate architecture is essential. There are some structures for this era which used specialization approach to cope with the limited power budget. Therefore, in this thesis, we propose a general-purpose platform that provides...
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