Loading...

Power-aware branch target prediction using a new BTB architecture

Sadeghi, H ; Sharif University of Technology

715 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/VLSISOC.2009.6041330
  3. Abstract:
  4. This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using SimpleScalar and Wattch performance and power tools. The simulation experiment results show that the first method decreases power about 3% and the second method decreases power consumption of BTB up to 7.3%. Moreover, combining these two methods would reduce power consumption of BTB up to 8.3% without affecting performance of the processor
  5. Keywords:
  6. Branch target buffer ; Performance analysis ; Power analysis ; Power consumption ; Branch prediction ; Current branch ; Data array ; Power tools ; Power-aware ; Prediction accuracy ; Simplescalar ; Simulation experiments ; Tag arrays ; Target prediction ; Forecasting
  7. Source: Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 ; 2011 , p. 53-58 ; ISBN: 9781457702365
  8. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6041330