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A low power 1.2 GS/s 4-bit flash ADC in 0.18 μm CMOS

Chahardori, M ; Sharif University of Technology | 2013

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  1. Type of Document: Article
  2. DOI: 10.1109/EWDTS.2013.6673204
  3. Publisher: 2013
  4. Abstract:
  5. A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS process
  6. Keywords:
  7. Converter structure ; Effective number of bits ; Monte-Carlo simulations ; Offset calibration ; Power reduction techniques ; Sampling rates ; Standard CMOS process ; Voltage generations ; CMOS integrated circuits ; Intelligent systems ; Calibration
  8. Source: Proceedings of IEEE East-West Design and Test Symposium, EWDTS 2013 ; 2013 ; 9781479920969 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6673204