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New approach to VLSI buffer modeling, considering overshooting effect

Mehri, M ; Sharif University of Technology | 2013

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  1. Type of Document: Article
  2. DOI: 10.1109/TVLSI.2012.2211629
  3. Publisher: 2013
  4. Abstract:
  5. In this brief, we use the alpha power law model for MOS devices to reach a more accurate modeling of CMOS buffers in very deep submicrometer technologies. We derive alpha model parameters of a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICE simulations. By analytical efforts we find the output resistance of a minimum-size buffer and compare it with those extracted from HSPICE simulations. We propose a new model for the output resistance of a given-size buffer in any technology, which demonstrates 3% error on average as opposed to the conventional model. Also a new buffer resistance is proposed analytically and numerically to calculate the crosstalk for interconnect analysis applications. In addition, we propose a model for the transfer function zero generated by the gate-drain capacitances of MOS transistors, which cause the overshooting effect, and develop an accurate expression for modeling this phenomenon. As the final point, together with the input-to-output capacitance, the equivalent output resistors present a simple and accurate macromodel for the CMOS buffer
  6. Keywords:
  7. CMOS buffer modeling ; Alpha-power law ; buffer overshooting effect ; CMOS buffer ; Conventional models ; Deep submicrometer technologies ; Gate-drain capacitance ; Interconnect analysis ; VLSI buffer ; Electric resistance ; Capacitance
  8. Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 21, Issue 8 , August , 2013 , Pages 1568-1572 ; 10638210 (ISSN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6293911