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Write invalidation analysis in chip multiprocessors

Ardalani, N ; Sharif University of Technology | 2010

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  1. Type of Document: Article
  2. DOI: 10.1007/978-3-642-11802-9_24
  3. Publisher: 2010
  4. Abstract:
  5. Chip multiprocessors (CMPs) issue write invalidations (WIs) to assure program correctness. In conventional snoop-based protocols, writers broadcast invalidations to all nodes as soon as possible. In this work we show that this approach, while protecting correctness, is inefficient due to two reasons. First, many of the invalidated blocks are not accessed after invalidation making the invalidation unnecessary. Second, among the invalidated blocks many are not accessed anytime soon, making immediate invalidation unnecessary. While invalidating the first group could be avoided altogether, the second group's invalidation could be delayed without any performance or correctness cost. Accordingly, we show that there exists an ample opportunity to eliminate and/or delay many WIs without harming performance or correctness. Moreover we investigate invalidation necessity and urgency and show that a large share of WIs could be delayed without impacting program outcome. Our study shows that WIs often repeats their behavior from both the necessity and urgency point of view. Finally we study how eliminating unnecessary WIs could potentially reduce bus occupancy
  6. Keywords:
  7. Chip multiprocessors ; Write Invalidation ; Cache coherency ; Chip Multiprocessor ; In-chip ; Program correctness ; Program outcomes ; Second group ; Multiprocessing systems ; Technical presentations ; Time measurement ; Timing circuits ; Systems analysis
  8. Source: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 9 September 2009 through 11 September 2009, Delft ; Volume 5953 LNCS , 2010 , Pages 196-205 ; 03029743 (ISSN) ; 3642118011 (ISBN)
  9. URL: http://link.springer.com/chapter/10.1007%2F978-3-642-11802-9_24