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Improving the Reliability of the STT-RAM Caches Against Transient Faults

Azad, Zahra | 2016

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 49123 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghassem
  7. Abstract:
  8. Cache memories occupy a large portion of processors chip area. According to academic and industrial reports, the dominant effect of leakage current in less than 40-nm technology nodes has led to serious challenges in scalability and energy consumption of SRAM and DRAM memories. To overcome this challenge, different types of non-volatile memories have been introduced. Among them, Spin-Transfer Torque Random Access Memory (STT-RAM) memory is known as the best candidate to replace SRAM in the cache memories, due to its high density and low access latency. Despite their advantages over SRAMs, several problems in STT-RAM need to be addressed to make it applicable in cache memories. The most important challenge in exploiting STT-RAM in cache memories is its considerable transient error rate. STT-RAM transient errors can be divided into three main categories: 1) write errors, 2) read disturbance errors, and 3) retention errors. The sources of these errors and the ways to cope with them are different. The most common way to decrease write errors, which are the focus of this study, is using Error Correcting Codes (ECCs). In this study, two ECC-based structures are proposed to reduce the cache protection overheads. In these structures, considering the asymmetric write error rates in switching of 0→1 and 1→0 and the dependency between the write error probability and the data content, cache blocks are protected heterogeneously based on their error rates. The proposed structures are evaluated using the gem5 simulator running 18 workloads from SPEC CPU2006 benchmark suite. The evaluation results show that besides providing the required reliability level, the first structure, so-called Asymmetry-Aware Protection Technique (A2PT), decreases the area and energy consumption overhead of ECC by 62% and 67%, respectively. In addition, A2PT reduces cache bit flips by 28%, which leads to about 24% reduction in write energy consumption. The second structure, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), reduces the ECC area and energy consumption overhead by about 81% and 72%, respectively. Furthermore, the performance overhead of both structures is less than 1% in comparison with the baseline structure
  9. Keywords:
  10. Nonvolatile Memory ; Cache Memory ; Spin Transfer Torque-Magnetic (STT-MRAM) ; Reliability ; Error Correction Codes ; Transient Error ; Write Error

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