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Efficient processor allocation in a reconfigurable CMP architecture for dark silicon era

Aghaaliakbari, F ; Sharif University of Technology | 2016

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  1. Type of Document: Article
  2. DOI: 10.1109/ICCD.2016.7753298
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2016
  4. Abstract:
  5. The continuance of Moore's law and failure of Dennard scaling force future chip multiprocessors (CMPs) to have considerable dark regions. How to use up available dark resources is an important concern for computer architects. In harmony with these changes, we must revise processor allocation schemes that severely affect the performance of a parallel on-chip system. A suitable allocation algorithm should reduce runtime and increase the power efficiency with proper thermal distribution to avoid hotspots. With this motivation, this paper proposes a power-efficient and high performance general purpose infrastructure for which a Dark Silicon Aware Processor Allocation (DSAPA) scheme is proposed which targets future many-core systems. To obtain high performance, we suggest a tunable-clustered mesh with the capability of sharing NoC resources in each cluster. We also employ a buffer-level power gating technique is used to improve power efficiency. Evaluation results reveal that the maximum achieved performance and power consumption improvements are 38.7% and 29.4% for multi-threaded workloads over the equivalent conventional design
  6. Keywords:
  7. Efficiency ; Reconfigurable architectures ; Allocation algorithm ; Chip multi-processors (CMPs) ; CMP architectures ; Computer architects ; Conventional design ; Evaluation results ; Processor allocation ; Thermal distributions ; Network-on-chip
  8. Source: Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016, 2 October 2016 through 5 October 2016 ; 2016 , Pages 336-343 ; 9781509051427 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/7753298