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An energy efficient 40 Kb SRAM module with extended read/write noise margin in 0.13μm CMOS
Sharifkhani, M ; Sharif University of Technology | 2009
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- Type of Document: Article
- DOI: 10.1109/JSSC.2008.2010815
- Publisher: 2009
- Abstract:
- Based on the dynamic criteria for data stability, we introduce segmented virtual grounding architecture with extended read, write noise margin to realize a low leakage current, energy efficient SRAM module. The architecture offers subthreshold operation for the entire module, except for the selected segments. In addition, a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation. The stability of the cells is enhanced in both read and write operation by controlling the cell access time and cell supply voltage, respectively. A 2048$, imes,$20 bit eSRAM unit is implemented in a regular 0.13 $muhbox{m} $ CMOS technology to confirm the idea. The unit operates at 100 MHz and consumes less than 1 mW in both read and write operations. Thanks to the reverse body bias of the transistors, the leakage current of a 0.4 V cell drops to 27 pA during the non-access time. The measurement results shows a 28% noise margin enhancement for this scheme when a subthreshold cell is accessed. © 2006 IEEE
- Keywords:
- CMOS integrated circuits ; Energy efficiency ; Integrated circuit layout ; Stability criteria ; Access time ; Bit-lines ; Body bias ; Cmos technologies ; Dynamic data stability ; Energy-efficient ; Low-leakage currents ; Low-power design ; Measurement results ; Noise margins ; Operational modes ; SRAM ; SRAM cells ; SRAM modules ; Sub thresholds ; Sub-threshold operations ; Supply voltages ; Write operations ; Static random access storage
- Source: IEEE Journal of Solid-State Circuits ; Volume 44, Issue 2 , 2009 , Pages 620-630 ; 00189200 (ISSN)
- URL: https://ieeexplore.ieee.org/document/4768891