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An efficient Protection Technique for last level STT-RAM caches in multi-core processors

Azad, Z ; Sharif University of Technology | 2017

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  1. Type of Document: Article
  2. DOI: 10.1109/TPDS.2016.2628742
  3. Publisher: IEEE Computer Society , 2017
  4. Abstract:
  5. Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAMseems to be themost promising alternative.With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches.High probability of write error due to stochastic switching is amajor problemin STT-RAMs. Conventional Error-CorrectingCodes (ECCs) impose significant area and energy consumption overheads to protect STT-RAMcaches. These overheads in multi-core processors with large last-level caches are not affordable. In this paper, we propose Asymmetry-Aware Protection Technique (A2PT) to efficiently protect the STT-RAMcaches. A2PT benefits from error rate asymmetry of STT-RAMwrite operations to provide the required level of cache protectionwith significantly lower overheads. Comparedwith the conventional ECC configuration, the evaluation results show that A2PT reduces the area and energy consumption overheads by about 42 and 50 percent, respectively, while providing the same level of protection.Moreover, A2PT decreases the number of bit switching in write operations by 28 percent, which leads to about 25 percent saving inwrite energy consumption. © 2016 IEEE
  6. Keywords:
  7. Asymmetric switching ; Error-correcting codes (ECCS) ; Multi-core processors ; Non-uniform protection ; Stt-ram caches ; Energy utilization ; Stochastic systems ; Efficient protections ; Error correcting code ; Multi-core processor ; Multi-core systems ; Non-uniform ; Protection techniques ; Stochastic switching ; Stt rams ; Errors
  8. Source: IEEE Transactions on Parallel and Distributed Systems ; Volume 28, Issue 6 , 2017 , Pages 1564-1577 ; 10459219 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/7744670