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Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance

Sakian, P ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1049/iet-cds:20080111
  3. Publisher: 2008
  4. Abstract:
  5. A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 μm CMOS technology and operating in 10 Gbps data rate, the entire circuit consumes 52 mW. © 2008 The Institution of Engineering and Technology
  6. Keywords:
  7. CMOS integrated circuits ; Jitter ; Analytical approaches ; Cdr systems ; Clock and data recoveries ; Clock generators ; Cmos technologies ; Control circuits ; Data rates ; Frequency control loops ; High frequencies ; Low powers ; Phase interpolators ; Power consumptions ; Tracking abilities ; Clocks
  8. Source: IET Circuits, Devices and Systems ; Volume 2, Issue 5 , 2008 , Pages 409-421 ; 1751858X (ISSN)
  9. URL: https://digital-library.theiet.org/content/journals/10.1049/iet-cds_20080111