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Enhanced TED: a new data structure for RTL verification

Lotfi Kamran, P ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1109/VLSI.2008.108
  3. Publisher: 2008
  4. Abstract:
  5. This work provides a canonical representation for manipulation of RTL designs. Work has already been done on a canonical and graph-based representation called Taylor Expansion Diagram (TED). Although TED can effectively be used to represent arithmetic expressions at the word-level, it is not memory efficient in representing bit-level logic expressions. In addition, TED cannot represent Boolean expressions at the word-level (vector-level). In this paper, we present modifications to TED that will improve its ability for bit-level logic representation while enhancing its robustness to represent word-level Boolean expressions. It will be shown that for bit-level logic expressions, the Enhanced TED (ETED) performs the same as the BDD representation. © 2008 IEEE
  6. Keywords:
  7. Arithmetic expressions ; Boolean expressions ; Canonical representations ; Graph-based representations ; International conferences ; Logic expressions ; Logic representation ; Memory efficient ; RTL designs ; RTL verification ; Taylor expansions ; VLSI designs ; Boolean algebra ; Boolean functions ; Data structures ; Digital signal processing ; File organization ; Fuzzy logic
  8. Source: 21st International Conference on VLSI Design, VLSI DESIGN 2008, Hyderabad, 4 January 2008 through 8 January 2008 ; 2008 , Pages 481-486 ; 0769530834 (ISBN); 9780769530833 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4450546