Loading...
Assertion-based debug infrastructure for SoC designs
Gharehbaghi, A.M ; Sharif University of Technology | 2007
379
Viewed
- Type of Document: Article
- DOI: 10.1109/ICM.2007.4497679
- Publisher: 2007
- Abstract:
- In this paper, an infrastructure for debug of complex SoCs that employs assertions is introduced. The proposed infrastructure combines traditional off-chip analysis techniques with on-chip at-speed debug facilities. The main part of on-chip debug hardware consists of data and transaction monitors. The monitor hardware is automatically generated by synthesizing the assertions that were used for verification and validation before manufacturing. We have integrated the proposed method in a system-level design methodology. By synthesizing various assertions from different kinds in a case study we have studied the overhead of our method. © 2007 IEEE
- Keywords:
- Data compression ; Microelectronics ; Assertion-based debug ; At-speed ; Automatically generated ; Debug infrastructure ; Off-chip analysis ; On chips ; SOC designs ; System on chip ; System-level designs ; Verification and validations ; Software design
- Source: 19th International Conference on Microelectronics, ICM, Cairo, 29 December 2007 through 31 December 2007 ; 2007 , Pages 137-140 ; 9781424418473 (ISBN)
- URL: https://ieeexplore.ieee.org/document/4497679