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Power analysis attacks on MDPL and DRSL implementations

Moradi, A ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1007/978-3-540-76788-6_21
  3. Publisher: Springer Verlag , 2007
  4. Abstract:
  5. Several logic styles such as Masked Dual-Rail Pre-charge Logic (MDPL) and Dual-Rail Random Switching Logic (DRSL) have been recently proposed to make implementations resistant against power analysis attacks. In this paper, it is shown that the circuits which contain sequential elements, flip-flops, and implemented in MDPL or DRSL styles are vulnerable to DPA attacks. Based on our results, the information leakage of CMOS D-flip-flops that are used to construct MDPL and DRSL D-flip-fiops is the cause of this vulnerability. To reduce the leakage, a modification on the structure of the MDPL and DRSL flip-flops are proposed; two CMOS D-flip-flops are used in the suggested structure. The proposed technique shows a significant reduction in the information leakage of MDPL and DRSL flip-flops. © Springer-Verlag Berlin Heidelberg 2007
  6. Keywords:
  7. Cryptography ; Formal logic ; DRSL ; Information leakage ; MDPL ; Side-channel attacks ; Flip flop circuits
  8. Source: 10th International Conference on Information Security and Cryptology, ICISC 2007, Seoul, 29 November 2007 through 30 November 2007 ; Volume 4817 LNCS , 2007 , Pages 259-272 ; 03029743 (ISSN); 9783540767879 (ISBN)
  9. URL: https://link.springer.com/chapter/10.1007%2F978-3-540-76788-6_21