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Enhancing A RISC-V Based Processor to Support Lattice-based Post-uantum Cryptography

Hadayeghparast, Shahriar | 2021

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 54373 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Bayat Sarmadi, Siavash
  7. Abstract:
  8. The amount of data over networks are increasing rapidly, and accordingly, smart devices are being encountered severe challenges by the advancement of security threats. In order to create safe communications among smart devices, employing public-key cryptography is needed. But, public-key and classic cryptography, such as RSA, have high computation complexities and are not resistant to quantum attacks. Due to mentioned reasons, using these types of cryptography algorithms in internet-of-things (IoT) devices is unreasonable. In the past decade, lattice-based cryptography has been one of the pioneer post-quantum cryptography members, which benefits from comparatively lower computational complexity that paves the way for being a convenient candidate for internet-of-things. Because of desirable properties, an efficient implementation based on the RISC-V architecture for one of the lattice-based cryptography variants, namely, inverse binary learning with errors over the ring, is proposed in this research. The proposed architecture implementation results on field-programmable gate arrays show at least a two times improvement compared to the prior works in terms of executive clock cycles. The proposed architecture has been designed for lightweight IoT devices and has 6% to 9% area overhead to the original RISC-V core. Besides, a technique for making the proposed architecture resistant against fault injection is presented in the dissertation with only 1% percent area overhead to the initial circuit. By carrying out an analysis of the proposed architecture regarding the hardware security principles, its resistance against timing and simple power analysis attacks will be substantiated. Eventually, reported results from application-specific integrated circuit's implementation demonstrate 10% and 13% power and area reduction compared to the best of the previous works, respectively
  9. Keywords:
  10. Post-Quantum Cryptography ; Learning with Error Problem ; Lattice-Based Cryptography ; Reduced Instruction Set Computer (RISC) ; Hardware Design

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