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A hardware approach to concurrent error detection capability enhancement in COTS processors

Rajabzadeh, A ; Sharif University of Technology | 2005

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  1. Type of Document: Article
  2. DOI: 10.1109/PRDC.2005.7
  3. Publisher: 2005
  4. Abstract:
  5. To enhance the error detection capability in COTS (commercial off-the-shelf) -based design of safety-critical systems, a new hardware-based control flow checking (CFC) technique will be presented. This technique, Control Flow Checking by Execution Tracing (CFCET), employs the internal execution tracing features available in COTS processors and an external watchdog processor (WDP) to monitor the addresses of taken branches in a program. This is done without any modification of application programs, therefore, the program overhead is zero. The external hardware overhead is about 3.5% using an Altera Flex 10K30 FPGA. For different workload programs, the execution time overhead and the error detection coverage of the technique vary between 33.3 and 140.8% and between 79.7 and 84.6% respectively. The errors are detected with about zero latency
  6. Keywords:
  7. Computer hardware ; Error detection ; Field programmable gate arrays (FPGA) ; Program processors ; Application programs ; External watchdog processor (WDP) ; Program execution ; Workload programs ; Software engineering
  8. Source: 11th Pacific Rim International Symposium on Dependable Computing, PRDC 2005, Changsha, Hunan, 12 December 2005 through 14 December 2005 ; Volume 2005 , 2005 , Pages 83-90 ; 0769524923 (ISBN); 9780769524924 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1607502?arnumber=1607502