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Fault detection enhancement in cache memories using a high performance placement algorithm

Zarandi, H. R ; Sharif University of Technology | 2004

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  1. Type of Document: Article
  2. DOI: 10.1109/OLT.2004.1319666
  3. Publisher: 2004
  4. Abstract:
  5. Data integrity of words coming out of the caches needs to be checked to assure their correctness. This paper proposes a cache placement scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is divided into sets of different sizes. Here, the length of tag fields associated to each set is unique and is different from the other sets. The other remained bits of tags are used for protecting the tag using a fault detection scheme e.g., generalized parity. This leads to protect the cache without compromising performance and area with respect to the similar one, fully associative cache. The results obtained from simulating some standard trace files reveal that the proposed scheme exhibits a performance near to fully associative but achieves a considerable fault detection coverage which is suitable to be used in the dependable computing
  6. Keywords:
  7. Fault detection ; Error correction codes ; Protection ; Bandwidth ; Cache memory ; Error correction ; Computer science ; Data engineering ; Physics computing ; High performance computing
  8. Source: Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004, Madeira Island, 12 July 2004 through 14 July 2004 ; 2004 , Pages 101-106 ; 0769521800 (ISBN); 9780769521800 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1319666