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A novel improvement technique for high-level test synthesis

Safari, S ; Sharif University of Technology | 2003

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  1. Type of Document: Article
  2. Publisher: 2003
  3. Abstract:
  4. Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iteration, and significant improved fault coverage. In this paper, we present a novel register allocation method, which is based on weighted graph coloring algorithm, targeting testability improvement for digital circuits. The topics covered in this paper include an overview of HLS and testability parameters, our testability model and experimental results
  5. Keywords:
  6. Conflict graph ; HLS ; Incompatible variables ; Register allocation ; Simulated annealing ; Weighted graph coloring
  7. Source: Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, Bangkok, 25 May 2003 through 28 May 2003 ; Volume 5 , 2003 , Pages V609-V612 ; 02714310 (ISSN)
  8. URL: https://ieeexplore.ieee.org/document/1206386