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Dependability analysis using a fault injection tool based on synthesizability of HDL models

Zarandi, H. R ; Sharif University of Technology | 2003

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  1. Type of Document: Article
  2. DOI: 10.1109/TSM.2005.1250147
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2003
  4. Abstract:
  5. This paper presents a fault injection tool, called SINJECT that supports several synthesizable and non-synthesizable fault models for dependability analysis of digital systems modeled by popular HDLs. The tool provides injection of transient and permanent faults into the Verilog as well as VHDL models of a digital circuit to study the fault behavior, fault propagation and fault coverage. Moreover, using specific simulators, the SINJECT provides a mixed-mode fault injection, i.e., fault injection into both Verilog and VHDL parts of a model, to achieve high description reality by Verilog and high capability modeling by VHDL. To demonstrate the tool, two case studies are evaluated: 1) an arithmetic processor with a non-synthesizable Verilog model, called ARP and 2) a VHDL model of 32-bit processor with a synthesizable ALU, called DP32. The results show that depending on the fault injection points in the ARP, the effects of faults were significantly different, while in the case of DP32, the fault coverage varied between 51 to 56 percent of total fault injected. © 2003 IEEE
  6. Keywords:
  7. Defects ; Software testing ; Reduced instruction set computing ; Fault tolerance
  8. Source: 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2003, 3 November 2003 through 5 November 2003 ; Volume 2003-January , 2003 , Pages 484-492 ; 15505774 (ISSN); 0769520421 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1250147