Loading...

Testability improvement during high-level synthesis

Safari, S ; Sharif University of Technology | 2003

138 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/ATS.2003.1250874
  3. Publisher: IEEE Computer Society , 2003
  4. Abstract:
  5. Improving testability during the early stages of High-Level Synthesis (HLS) reduces test hardware overheads, test costs, design iterations, and also improves fault coverage. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement. © 2003 IEEE
  6. Keywords:
  7. High-level synthesis ; Logic circuit testing ; Graph theory ; Design for testability
  8. Source: 12th Asian Test Symposium, ATS 2003, 16 November 2003 through 19 November 2003 ; Volume 2003-January , 2003 , Pages 505- ; 10817735 (ISSN); 0769519512 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1250874