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Testability improvement during high-level synthesis
Safari, S ; Sharif University of Technology | 2003
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- Type of Document: Article
- DOI: 10.1109/ATS.2003.1250874
- Publisher: IEEE Computer Society , 2003
- Abstract:
- Improving testability during the early stages of High-Level Synthesis (HLS) reduces test hardware overheads, test costs, design iterations, and also improves fault coverage. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement. © 2003 IEEE
- Keywords:
- High-level synthesis ; Logic circuit testing ; Graph theory ; Design for testability
- Source: 12th Asian Test Symposium, ATS 2003, 16 November 2003 through 19 November 2003 ; Volume 2003-January , 2003 , Pages 505- ; 10817735 (ISSN); 0769519512 (ISBN)
- URL: https://ieeexplore.ieee.org/document/1250874