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A 3.3 V/1 W class D audio power amplifier with 103 dB DR and 90% efficiency

Tousi, V. M ; Sharif University of Technology | 2002

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  1. Type of Document: Article
  2. DOI: 10.1109/MIEL.2002.1003324
  3. Publisher: IEEE Computer Society , 2002
  4. Abstract:
  5. A single-chip Integrated circuit of 3.3 V/1 W class-D high fidelity and high efficiency audio power amplifier is presented in this paper. The design has been done using a 3.3 V/0.25 /spl mu/m CMOS process. The maximum output power is 1 W before the amplifier saturates. The THD+N at 0.5 W output power is below 0.03% and efficiency is better than 90% thanks to the careful design of the output stage. The dynamic range is more than 100 dB suitable for high fidelity audio applications. A single-loop single-bit third order sigma-delta modulator is used to generate the PWM signal from input audio signal. The PWM signal is then filtered at the output with a second order low pass filter external to the chip to regenerate the input signal. © 2002 IEEE
  6. Keywords:
  7. Power amplifiers ; Signal generators ; Power generation ; Energy consumption ; Inductors ; High power amplifiers ; Switching frequency ; Pulse width modulation inverters ; Delta-sigma modulation ; Pulse width modulation
  8. Source: 2002 23rd International Conference on Microelectronics, MIEL 2002, Nis, 12 May 2002 through 15 May 2002 ; Volume 2 , 2002 , Pages 581-584 ; 0780372352 (ISBN); 9780780372351 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1003324