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Improvement of the in-Memory Automata Processor Accelerators using Emerging Memories

Yazdanpanah, Ali | 2023

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 56120 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hessabi, Shahin
  7. Abstract:
  8. Non-deterministic finite automata (NFA) are an elementary type of Turing machines with very high processing power. NFA processors provide parallelism at the data and task level because they can be in several different output states in one clock cycle. Implementing such machines with memory is a good strategy because if we consider each of the memory columns as a state, by selecting a row of the memory, we can activate several states at the same time, which is an implementation of NFA. NFA-based automata processors were first introduced by Micron and were very powerful for issues such as pattern matching, DNA sequencing, or regular expressions and, in general, for machine learning topics. Processing in such machines is not unlike conventional processing and is based on the use of memories (Memory-centric computing).In-memory computing provides a very good platform for fast processing due to the removal of data movement overhead from memory to the processing system and vice versa. In addition, emerging memory technologies make it possible to design accelerators with higher processing speed, less energy consumption overhead, and less area than other hardware accelerators. The hardware resources inside the memory systems and their logic cells are limited, so we need to design high-performance accelerators with low hardware area, leakage power, and low energy consumption. This Thesis introduces an architecture called MAP using magneto-resistive multilevel SOT-STT MRAM memory cells, which serve as an improved automata processor platform that enables the design of an in-memory automata processor accelerator. Essential parameters such as memory read latency, dynamic read energy, leakage power, the occupied area of memory، and other factors are greatly improved by using emerging SOT-STT MRAM memories. From the point of view of an automata processor, the MAP architecture averages between 2.3 and 40 times less latency, between 9 and 15 times less leakage power, between 2.6 and 3.8 times less area, and between 1.05 and 40 times less power consumption than the best automata processors in the recent researches
  9. Keywords:
  10. Automata Processors ; Spin Transfer Torque-Magnetic (STT-MRAM) ; SOT-STT MRAM Magneto-Resistive Memory ; Memory-Centric Computing ; Automata Accelerator ; In-Memory Computing

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