Reducing the Energy Consumption of the Embedded Real-Time Systems with Reconfigurable Components

Dastangoo, Ali | 2010

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 40763 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Ejlali, Alireza
  7. Abstract:
  8. Over the Recent Decade, the embedded systems have expanded to include a wide variety of products, ranging from digital cameras, to medical systems, to Radar and telecommunication systems, to sensor networks. Engineers strive to create ever smaller and faster products, many of which, such as battery operated systems, have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Dynamic reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems. SRAM-based FPGAs are a good instance of dynamic reconfigurable hardware. These chips are reconfigurable to target configuration at runtime to implement many necessary functions. In contrast to ASIC, designing with FPGAs are very convenient and cheap, so that design and synthesis time totally last from a few weeks to a few months. Design faults are easily eliminated by loading correct configuration, without any additional cost. Since mid-1990s, coupled processor-FPGA systems have become a prevalent architecture. Hardware is needed for its high performance and processor for running Operating System. Consequently many researches have been performed to effective using of hardware to reduce time and energy. Besides, compute-intensive tasks exist in many real-time signal processing and multi-media applications such that processors aren’t able to complement those tasks before deadline. This problem even exist when we using a digital signal processor alone. We have considered energy-optimized scheduling for a duplex system that consists of coupled processor and FPGA, analytically. Next, we develop a scheduling algorithm that results in minimum energy for specified deadline and run time information of two implementations. Deadlines always are met even when second execution required to be complemented because of a fault occur on first execution. Another benefit of this system is; because of very diverse implementation of duplex system, in compare with two processor (same or different) duplex system, our system is very resistance to common mode failure. Although we have proved that energy of our algorithm is minimum, however, for evaluating our approach, we have compared it with a greedy algorithm and we observe our algorithm is in average 28.8% better than greedy algorithm
  9. Keywords:
  10. Energy Management ; Embedded Real-Time System ; Dynamic Reconfiguration ; Reconfigurable Hardware ; Duplex System

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