Design of a DLL-Based Frequency Synthesizer for Wireless Recievers<br/>

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Design of a DLL-Based Frequency Synthesizer for Wireless Recievers

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 41159 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Sharif Khani, Mohammad; Atarodi, Mojtaba
Abstract:
A DLL-based frequency synthesizer that has the capability of producing fractional multiples of the reference frequency is designed and implemented in this thesis. The new structures for producing fractional multiples of reference frequency with DLLs are also presented. The designed frequency synthesizer is not a Sigma-delta modulator for synthesizing. This structure has a low jitter and phase-noise, low chip area, low settling time and a good stability due to its DLL-based nature. Also, a systematic model for simulating DLLs in MATLAB Simulink is proposed that is very efficient for giving a better insight to designing of DLLs. The settling time of the proposed topology for DLL is 2.5us. The worst case power consumption is 2.8mW. The used CMOS technology is 0.13um with a 1.2 power supply. This synthesizer can be used in wireless communication systems, satellite receivers and optical transceivers
Keywords:
Delog Locked Loop ; Phase Noise ; Timing Jitter ; Frequency Synthesizer ; Fractional Multiples

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