An efficient technique to tolerate MBU faults in register file of embedded processors

Abazari, M. A ; Sharif University of Technology | 2012

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  1. Type of Document: Article
  2. DOI: 10.1109/CADS.2012.6316430
  3. Publisher: 2012
  4. Abstract:
  5. This paper presents a Data Width-aware Register file Protection (DWRP) technique to cope with Multiple Bit Upsets (MBUs) occurring in the register file of embedded processors. The DWRP technique has been proposed based on the fact that there are often a significant number of bits in the register file, which are not fully occupied by data. The DWRP technique efficiently exploits these available free bits for reliability enhancement purposes. In this regard, every register is equipped with three extra tag bits to specify the amount of available free bits in a register. Then the appropriate parity or hamming code is used based on the information of the tag field to protect the register file against MBUs. The DWRP technique is extensively evaluated on an HDL model of an ARM embedded processor along with various MBU fault injection experiments. Experimental results show that the DWRP technique detects up to 99% of MBUs with average length of 16 bits. These are achieved with negligible overheads of 7% in area and 1% in power consumption of the evaluated processor
  6. Keywords:
  7. Average length ; Embedded processors ; Fault injection ; Hamming code ; HDL models ; Multiple bit upset ; Register files ; Reliability enhancement ; Computer architecture
  8. Source: CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 115-120 ; 9781467314824 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6316430

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