Loading...
A low cost circuit level fault detection technique to full adder design
533 viewed

A low cost circuit level fault detection technique to full adder design

Mozafari, S. H

A low cost circuit level fault detection technique to full adder design

Mozafari, S. H ; Sharif University of Technology | 2011

533 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/ICECS.2011.6122309
  3. Publisher: 2011
  4. Abstract:
  5. This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition
  6. Keywords:
  7. Full adder ; Low area ; Low power ; Adder circuit ; Basic elements ; Circuit levels ; Detection coverage ; Detection latency ; Fault detection techniques ; Fault injection ; Full adders ; low area ; Low cost circuit ; Low Power ; Error detection ; Fault detection ; Adders
  8. Source: 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011, Beirut ; 2011 , Pages 446-450 ; 9781457718458 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6122309