Traffic-aware buffer reconfiguration in on-chip networks

Bashizade, R ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1109/VLSI-SoC.2015.7314416
  3. Publisher: IEEE Computer Society , 2015
  4. Abstract:
  5. Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications, respectively, with respect to the conventional state-of-the-art router
  6. Keywords:
  7. Network-on-chip ; Reconfigurable hardware ; Routers ; Average packet latencies ; Buffering requirements ; Chip multi-processors (CMPs) ; Networks on chips ; On-chip networks ; Reconfigurable ; State of the art ; Traffic pattern ; Programmable logic controllers
  8. Source: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 5 October 2015 through 7 October 2015 ; Volume 2015-October , 2015 , Pages 201-206 ; 23248432 (ISSN) ; 9781467391405 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7314416