Using intra-line level pairing for graceful degradation support in PCMs

Asadinia, M ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1109/ISVLSI.2015.94
  3. Publisher: IEEE Computer Society , 2015
  4. Abstract:
  5. In Phase-Change Memory (PCM), the number of writes a cell can take before wearing-out is limited and highly varied due to unbalanced write traffic and process variation. After the failure of weak cells and in presence of large number of failed lines, some techniques have been proposed to further prolong the lifetime of a PCM device by remapping failed lines to spares and salvage a PCM device with graceful degradation. Others rely on handling failures through inter-line pairing. Observations reveal that most of cells in a line are healthy when the line is marked as faulty by any of these proposals. To overcome this deficiency, we propose Intra-line Level Pairing(ILP), a technique that mitigates the problem of fast failure of lines by coupling faulty parts of a line onto other healthy parts of the same line. The target part of the line is programmed in the Multi-Level Cell (MLC) mode to keep data of both the faulty and target parts. Evaluation results for multi-threaded and multi-program workloads reveal noticeable improvement in time-to-failure and performance over existing techniques. Note that ILP is also orthogonal to all known line-level and page-level techniques
  6. Keywords:
  7. Intra line level Pairing ; Multi-level cell ; Cells ; Cytology ; Evaluation results ; Graceful degradation ; Multi level cell (MLC) ; Multithreaded ; Process Variation ; Time to failure ; Phase change memory
  8. Source: Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 8 July 2015 through 10 July 2015 ; Volume 07-10-July-2015 , 2015 , Pages 527-532 ; 21593469 (ISSN) ; 9781479987184 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7309625