Leveraging dark silicon to optimize networks-on-chip topology

Modarressi, M ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1007/s11227-015-1448-2
  3. Publisher: Kluwer Academic Publishers , 2015
  4. Abstract:
  5. This paper presents a reconfigurable network-on-chip (NoC) for many-core chip multiprocessors (CMPs) in the dark silicon era, where a considerable part of high-end chips cannot be powered up due to the power and bandwidth walls. Core specialization, which trades off the cheaper silicon area with energy-efficiency, is a promising solution to the dark silicon challenge. This approach integrates a selection of many diverse application-specific cores into a single many-core chip. Each application then activates those cores that best match its processing requirements. Since active cores may not always form a contiguous active region in the chip, such a partially active many-core CMP requires some special on-chip communication support to optimize NoC parameters for the current set of active cores. In this paper, we propose a reconfigurable NoC that leverages inactive routers of a many-core chip to customize the topology for active cores. In this design, routers of the dark part of the chip are used as bypass switches that can set up virtual long links between distant active nodes in the network. Our experimental results show considerable reduction in NoC energy consumption and latency
  6. Keywords:
  7. Dark silicon ; Networks-on-chip ; Energy efficiency ; Energy utilization ; Microprocessor chips ; Routers ; Silicon ; Topology ; VLSI circuits ; Active regions ; Bypass switches ; Dark silicons ; Diverse applications ; Networks on chips ; On chip communication ; Reconfigurable ; Reconfigurable network ; Network-on-chip
  8. Source: Journal of Supercomputing ; Volume 71, Issue 9 , 2015 , Pages 3549-3566 ; 09208542 (ISSN)
  9. URL: http://link.springer.com/article/10.1007/s11227-015-1448-2