FPGA-based protection scheme against hardware trojan horse insertion using dummy logic

Khaleghi, B ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1109/LES.2015.2406791
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2015
  4. Abstract:
  5. Hardware trojan horses (HTH) have recently emerged as a major security threat for field-programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may still leave a considerable amount of logic resources to be misused by malicious attacks. This letter presents a low-level HTH protection scheme for FPGAs by filling the unused resources with the proposed dummy logic. In the proposed scheme, we identify the unused resources at the device layout-level and offer dummy logic cells for different resources. The proposed HTH protection scheme has been applied on Xilinx Virtex devices implementing a set of IWLS benchmarks. The results show that by employing the proposed HTH protection scheme, the chance of logic abuse can be significantly reduced. Experimental results also show that as compared to nonprotected designs, the proposed HTH scheme imposes no performance and power penalties
  6. Keywords:
  7. Design for hardware trust ; Field-programmable gate arrays (FPGAs) ; Field programmable gate arrays (FPGA) ; Hardware ; Logic devices ; Logic gates ; Malware ; Microprocessor chips ; Network security ; Device layout ; Hardware Trojan horse ; Logic resources ; Malicious attack ; Power penalty ; Protection schemes ; Security threats ; Xilinx Virtex devices ; Hardware security
  8. Source: IEEE Embedded Systems Letters ; Volume 7, Issue 2 , 2015 , Pages 46-50 ; 19430663 (ISSN)
  9. URL: http://ieeexplore.ieee.org/document/7047801