Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design

Zare, M ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1049/iet-cdt.2013.0121
  3. Publisher: Institution of Engineering and Technology , 2015
  4. Abstract:
  5. Delay in communication wires causes design iterations in system-on-chip. Latency-insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling-based latency-insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm steps are described and the accuracy is validated through several synthetic benchmarks as well as real systems. Simulation results show an average 44.7% reduction on the shift registers area and the synthetic analysis in the authors proposed approach show an average 12.8% reduction on the total system area compared with the existing method
  6. Keywords:
  7. Algorithms ; Application specific integrated circuits ; Clocks ; Design ; Heuristic algorithms ; Heuristic methods ; Integrated circuit design ; Microprocessor chips ; Shift registers ; System-on-chip ; Wire ; Bit sequences ; Communication wire ; Design iteration ; Latency-insensitive designs ; Optimisations ; Real systems ; Synthetic analysis ; Synthetic benchmark ; Scheduling
  8. Source: IET Computers and Digital Techniques ; Volume 9, Issue 3 , May , 2015 , Pages 165-174 ; 17518601 (ISSN)
  9. URL: http://ieeexplore.ieee.org/document/7101894