Secure Implementation of Cryptographic Algorithms on FPGA

Farzam, Mohammad-Hossein | 2016

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 48811 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Bayat-Sarmadi, Siavash
  7. Abstract:
  8. Security of cryptographic devices lies amongst the most important issues in the field of hardware security. It is frequently seen that in the process of designing cryptographic systems insufficient attention is paid to the physical implementation details. This is happening while a lot of secret information is known to be leaked through side-channels such as power consumption, electromagnetic emission and execution time. Side-channel attacks are able to reveal secret keys by using these side-channel leakages. Additionally, side-channel attacks are one of the most powerful but low-cost attacks that put the security of cryptographic systems in vain. It can be claimed that the most dangerous property of these attacks is that they leave no evidence of the attack behind. FPGAs and smartcards are two of the most common platforms in cryptographic applications. Several studies have been performed on the security of implementations of cryptographic algorithms on these two platforms. Most of these studies in the national universities have favored simulation rather than practical experiment. The goal in the current study is to practically evaluate the security of implementations of cryptographic algorithms against power analysis attacks. To reach this end, specific instruments of such side-channel analyses have been used. Sakura-X, SASEBO-W and Picoscope 6403D are the most important instruments between them. The implementations of four cryptographic algorithms including AES, DES, TDES and RSA have been evaluated on both platforms. Experimental results show that cryptographic subkeys can be revealed by using 700, 400, 400 and 5,000 power traces, respectively. In the next level, several countermeasures have been applied to the implementations and the evaluation process has been repeated. The second evaluation using 100,000 power traces shows that the implementations of these algorithms are immune to power analysis attacks based on hamming distance model when masking is properly employed
  9. Keywords:
  10. Cryptography ; Hardware Security Module ; Power Analysis ; Field Programmable Gate Array (FPGA) ; Reconfigurable Devices ; Side Channel Attacks ; Power Analysis Attacks

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