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A wide dynamic range low power 2× time amplifier using current subtraction scheme

Molaei, H ; Sharif University of Technology | 2016

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  1. Type of Document: Article
  2. DOI: 10.1109/ISCAS.2016.7527277
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2016
  4. Abstract:
  5. The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2× TA is expanded to 300ps only with 9% gain error while it consumes only 28uW from a 1.2V supply voltage. © 2016 IEEE
  6. Keywords:
  7. ADPLL ; Frequency converters ; Reconfigurable hardware ; Dynamic range ; High resolution ; Time amplifier ; Time to digital converters ; Amplifiers (electronic)
  8. Source: 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, 22 May 2016 through 25 May 2016 ; Volume 2016-July , 2016 , Pages 462-465 ; 02714310 (ISSN); 9781479953400 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/7527277/?arnumber=7527277&tag=1