BLESS: A simple and efficient scheme for prolonging PCM lifetime

Asadinia, M ; Sharif University of Technology | 2016

388 Viewed
  1. Type of Document: Article
  2. DOI: 10.1145/2897937.2897993
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2016
  4. Abstract:
  5. Limited endurance problem and low cell reliability are main challenges of phase change memory (PCM) as an alternative to DRAM. To further prolong the lifetime of a PCM device, there exist a number of techniques that can be grouped in two categories: 1) reducing the write rate to PCM cells, and 2) handling cell failures when faults occur. Our experiments confirm that during write operations, an extensive non-uniformity in bit ips is exhibited. To reduce this non-uniformity, we present byte-level shifting scheme (BLESS) which reduces write pressure over hot cells of blocks. Additionally, this shifting mechanism can be used for error recovery purpose by using the MLC capability of PCM and manipulating the data block to recover faulty cells. Evaluation results for multi-threaded workloads reveal 14-25% improvement in lifetime over existing state-of-the-art schemes. © 2016 ACM
  6. Keywords:
  7. Fault tolerant ; Hard error ; Lifetime ; Cells ; Computer aided design ; Cytology ; Dynamic random access storage ; Molecular biology ; Efficient schemes ; Evaluation results ; Fault-tolerant ; Hard errors ; Phase change memory (pcm) ; State-of-the-art scheme ; Write operations ; Phase change memory
  8. Source: 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, 5 June 2016 through 9 June 2016 ; Volume 05-09 , June-2016 , 2016 ; 0738100X (ISSN); 9781450342360 (ISBN)
  9. URL: http://dl.acm.org/citation.cfm?doid=2897937.2897993