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A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application

Molaei, H ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/ICECS.2015.7440272
  3. Publisher: Institute of Electrical and Electronics Engineers Inc
  4. Abstract:
  5. A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively
  6. Keywords:
  7. Analog-to-digital converter ; Low power ; Sigma-Delta modulation ; Successive approximation register ; Approximation theory ; Comparator circuits ; Comparators (optical) ; Delta modulation ; Delta sigma modulation ; Digital to analog conversion ; Frequency converters ; Reconfigurable hardware ; Analog to digital converters ; Clock cycles ; Flash Analog-to-digital Converters ; Low Power ; SAR ADC ; Sigma delta ADC ; Successive approximation register ; Supply voltages ; Analog to digital conversion
  8. Source: IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016-March , 2016 , Pages 153-156 ; 9781509002467 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/7440272