A fine-grained configurable cache architecture for soft processors

Biglari, M ; Sharif University of Technology

619 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/CADS.2015.7377783
  3. Publisher: Institute of Electrical and Electronics Engineers Inc
  4. Abstract:
  5. The ever increasing density and performance of FPGAS, has increased the importance and popularity of soft processors. The growing gap between the speed of processors and memories can partly be compensated through memory hierarchy. Since memory accesses follow a non-uniform distribution, and vary from one application to another, variable set-associative cache architectures have emerged. In this paper, a novel cache architecture, primarily aimed at soft processors, is proposed to address the variable access demands of applications, through dynamically configurable line-associativity, with no memory overhead. The FPGA implementation of the proposed architecture achieves an average miss count reduction of 70% compared to the direct-mapped cache which translates in 17% improvement in IPC, on 11 benchmarks
  6. Keywords:
  7. FPGA ; Buffer storage ; Cache memory ; Energy efficiency ; Field programmable gate arrays (FPGA) ; Memory architecture ; Reconfigurable hardware ; Configurable cache ; Direct mapped cache ; FPGA implementations ; Non-uniform distribution ; Performance ; Proposed architectures ; Set associative cache ; Soft processors ; Computer architecture
  8. Source: 18th CSI International Symposium on Computer Architecture and Digital Systems, 7 October 2015 through 8 October 2015 ; 2015 ; 9781467380232 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/7377783