A high density and low power cache based on novel SRAM cell

Azizi Mazreah, A ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. Publisher: 2009
  3. Abstract:
  4. Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS five-transistor SRAM cell (5T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. Novel 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 17% smaller than a conventional six-transistor SRAM cell using same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during read/write and also the average dynamic energy consumption of new cell is 30% smaller than a six-transistor SRAM cell. © 2009 ACADEMY PUBLISHER
  5. Keywords:
  6. Cell area ; Dynamic energy consumption ; Read static noise margin free ; 5T SRAM cell ; Cell current ; Buffer storage ; Cell membranes ; Cytology ; Feedback ; Static random access storage
  7. Source: Journal of Computers ; Volume 4, Issue 7 , 2009 , Pages 567-575 ; 1796203X (ISSN)
  8. URL: https://www.jstage.jst.go.jp/article/elex/6/15/6_15_1084/_article/-char/en