An accurate low-power DAC for SAR ADCs

Yazdani, S. B ; Sharif University of Technology | 2017

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  1. Type of Document: Article
  2. DOI: 10.1109/MWSCAS.2016.7870003
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2017
  4. Abstract:
  5. A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. © 2016 IEEE
  6. Keywords:
  7. DAC ; Low-power ; SAR ADC ; Analog to digital conversion ; Bins ; Energy efficiency ; Accurate DAC ; Analogue to digital converters ; Highly energy efficiencies ; Least significant bits ; Low Power ; Successive approximation register ; Switching procedures ; Digital to analog conversion
  8. Source: 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/7870003