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Time to Digital Converters for ADPLL Applications

Molaei, Hasan | 2018

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 51950 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Hajsadeghi, Khosrow
  7. Abstract:
  8. Effect of resolution of Time to Digital Converters (TDCs) on the performance of All-Digital Phase Locked Loops (ADPLLs) and capability of achieving higher resolution in advanced technologies lead to introducing different kinds of TDCs. Beside the analysis of different kinds of TDCs, This thesis proposes three new TDCs based on the time amplifi-cation concept. A new pipeline TDC is designed using a wide dynamic range time amplifi-er. A new method is used to widen dynamic range of the conventional time amplifiers. In order to get a low power high resolution conversion, a new delay element design is devel-oped to reduce the delay value and its sensitivity to mismatch and process variations. Be-sides, a two-step TDC is presented using a new gain reconfigurable time amplifier. The TDC saves power by deactivating time amplifiers regarding to the input time difference. At last, a hybrid two-step TDC based on time-to-voltage conversion is designed. The TDC achieves not only low power conversion but also good linearity because of using a calibra-tion circuit for the time amplifier. In addition, a new hybrid comparator reduced Analog to Digital Converter (ADC) is proposed for the fine part of the TDC which make a good trade-off between speed and power consumption. All the proposed TDCs are designed and simulated in 0.18µm CMOS technology. Simulation results prove efficiency of the pro-posed TDCs for ADPLLs applications
  9. Keywords:
  10. Time to Digital Converter ; All Digital Phase Locked Loop ; Time Amplifier ; Delay Elements ; Low Power System ; Analog to Digital Converter

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