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A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology

Heydarzadeh, S ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1016/j.mejo.2019.04.018
  3. Publisher: Elsevier Ltd , 2019
  4. Abstract:
  5. A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The core chip occupied 400 μm × 702 μm area and consumed 2.1 mA current. © 2019 Elsevier Ltd
  6. Keywords:
  7. 65 nm CMOS technology ; Digitally Controlled Oscillator (DCO) ; Integrated Digital to Analog Converter ; Jitter measurement ; Linearity ; CMOS integrated circuits ; Digital to analog conversion ; IEEE Standards ; Jitter ; 65 nm CMOS technologies ; CMOS technology ; Digitally controlled oscillators ; Jitter measurements ; Offset frequencies ; Output frequency ; Wireless application ; Phase noise
  8. Source: Microelectronics Journal ; Volume 90 , 2019 , Pages 48-57 ; 00262692 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/abs/pii/S0026269219300102