Post-quantum cryptoprocessors optimized for edge and resource-constrained devices in IoT

Ebrahimi, S ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/JIOT.2019.2903082
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. By exponential increase in applications of the Internet of Things (IoT), such as smart ecosystems or e-health, more security threats have been introduced. In order to resist known attacks for IoT networks, multiple security protocols must be established among nodes. Thus, IoT devices are required to execute various cryptographic operations, such as public key encryption/decryption. However, classic public key cryptosystems, such as Rivest-Shammir-Adlemon and elliptic curve cryptography are computationally more complex to be efficiently implemented on IoT devices and are vulnerable regarding quantum attacks. Therefore, after complete development of quantum computing, these cryptosystems will not be secure and practical. In this paper, we propose InvRBLWE, an optimized variant for binary learning with errors over the ring (Ring-LWE) scheme that is proven to be secure against quantum attacks and is highly efficient for hardware implementations. We propose two architectures for InvRBLWE: 1) a high-speed architecture targeting edge and powerful IoT devices and 2) an ultralightweight architecture, which can be implemented on resource-constrained nodes in IoT. The proposed architectures are scalable regarding security levels and we provide experimental results for two versions of the InvRBLWE scheme providing 84 and 190 bits of classic security. Our implementation results on field programmable gate array dominate the best of the classic and post-quantum previous implementations. Moreover, our two different application specific integrated circuit (ASIC) implementations show improvement in terms of speed, area, power, and/or energy. To the best of our knowledge, we are the first to implement learning with error-based cryptosystems on ASIC platform. © 2014 IEEE
  6. Keywords:
  7. Hardware implementation ; Post-quantum cryptography ; Ring learning with errors (Ring-LWEs) ; Application specific integrated circuits ; Constrained optimization ; Errors ; Field programmable gate arrays (FPGA) ; Hardware security ; Health risks ; Network architecture ; Network protocols ; Network security ; Public key cryptography ; Quantum computers ; Quantum cryptography ; Hardware implementations ; Internet of Things (IOT) ; Lattice-based cryptography ; Learning with Errors ; Post quantum cryptography ; Internet of things
  8. Source: IEEE Internet of Things Journal ; Volume 6, Issue 3 , 2019 , Pages 5500-5507 ; 23274662 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8660431