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Design and Implementation of a 1-2 GHz Ultra Low Phase Noise Phase Locked Loop using SPD

Abedanzadeh, Amir Hossein | 2020

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 53999 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Banaei, Ali
  7. Abstract:
  8. In this thesis first of all we investigate phase noise and it's generation factors. Then we design and implement an ultra low phase noise oscillator. To do this, an ultra low phase noise oscillator which is tunable in 1-2GHz with 100MHz steps will be designed. The outline of the circuit is as follows: at the first we design a VCO which is ultra low phase noise and mechanically tunable in 1-2GHz by means of rotation of a handle. Then a phase locked loop will be built with the help of an ultra low phase noise OCXO at 100MHz and one SPD1 which generates harmonics of OCXO's output frequency. For the next, design and implementation of a 1.6GHz oscillator with fixed output frequency has been done. We achieve -100dBc/Hz phase noise level for 1kHz offset from center frequency of 1.6GHz for this oscillator.
  9. Keywords:
  10. Sampling Phase Detector ; Phase Locked Loop (PLL) ; Oscillators ; Phase Noise ; Volatile Organic Compound (VOC)

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