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A compact low power mixed-signal equalizer for gigabit ethernet applications

Mehrmanesh, S ; Sharif University of Technology | 2006

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  1. Type of Document: Article
  2. DOI: 10.1109/ISCAS.2006.1693796
  3. Publisher: 2006
  4. Abstract:
  5. In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter's coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 um CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply. © 2006 IEEE
  6. Keywords:
  7. Analog front end ; Mixed-signal linear equalizers ; Rotating structures ; Circuit simulation ; Computational complexity ; Digital to analog conversion ; Ethernet ; FIR filters ; Frequency multiplying circuits ; Signal receivers ; Equalizers
  8. Source: ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 21 May 2006 through 24 May 2006 ; 2006 , Pages 5167-5170 ; 02714310 (ISSN); 0780393902 (ISBN); 9780780393905 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1693796