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    Design of low power comparator-reduced hybrid ADC

    , Article Microelectronics Journal ; Volume 79 , 2018 , Pages 79-90 ; 00262692 (ISSN) Molaei, H ; Hajsadeghi, K ; Khorami, A ; Sharif University of Technology
    Elsevier Ltd  2018
    Abstract
    This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s... 

    A low-power comparator-reduced flash ADC using dynamic comparators

    , Article 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, 5 December 2017 through 8 December 2017 ; Volume 2018-January , 2018 , Pages 5-8 ; 9781538619117 (ISBN) Molaei, H ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    This paper presents a new low-power reduced comparator flash ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce offset and kick-back noise effect of conventional dynamic comparators, a new comparator with a higher pre-amplifier gain along with the mathematical analysis is presented. The proposed 4bit ADC is simulated in 0.18um with 1.8-υ supply voltage. SNDR and SFDR of the ADC are 23dB and 26.5dB, respectively. The ADC consumes only 0.95mw at the sampling rate of 400MS/s. © 2017 IEEE  

    Fast static characterization of residual-based ADCs

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 60, Issue 11 , 2013 , Pages 746-750 ; 15497747 (ISSN) Hassanpourghadi, M ; Sharifkhani, M ; Sharif University of Technology
    2013
    Abstract
    Computationally exhaustive time-domain Monte Carlo (MC) simulations are commonly conducted to obtain the static characteristics of a residual analog-to-digital converter (ADC) (e.g., pipelined ADC) for the calculation of the integral nonlinearity (INL) and differential nonlinearity (DNL). In this brief, a new ultrahigh-speed, yet precise, behavioral-level dc characterization algorithm for residual-based ADC is introduced. The algorithm derives the transition points of a given stage of the ADC based on the random parameters of that stage. Then, it merges the dc characteristics of all stages together to extract detailed dc input-output characteristics for the entire ADC. Then, the exact amount... 

    A 12-bit, 40MS/s, Low Power Pipelined SAR ADC

    , M.Sc. Thesis Sharif University of Technology Khojasteh Lazarjan, Vahid (Author) ; Haj Sadeghi, Khosro (Supervisor)
    Abstract
    High resolution and low power analog to digital converters are used in wireless communication receivers, Sensor Networks and Medical Instrumentations. Reducing power consumption at a high conversion rate is one of the most basic challenges for these converters. Pipelined SAR structure is considered for 40-50 MS/s and 10-12 bits, and is of interest because of consuming low power and using a small area. Besides using Pipelined SAR structure, circuit level and system level modifications are also proposed to decrease the power consumption. The ADC is designed in 0.18µm CMOS technology with 1.2v supply voltage. The results show 4.5mW power consumption, when ENOB is 11.04bit, which is very low... 

    A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application

    , Article IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016-March , 2016 , Pages 153-156 ; 9781509002467 (ISBN) Molaei, H ; Khorami, A ; Eslampanah Sendi, M. S ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc 
    Abstract
    A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

    Design of a High Resolution Sigma-Delta Modulator

    , M.Sc. Thesis Sharif University of Technology Mesgarani, Ali (Author) ; Haj Sadeghi, Khosro (Supervisor)
    Abstract
    Sigma-delta modulators have largely been implemented as discrete-time (DT) circuits because of their low sensitivity to circuit nonidealities, and their frequency scaling specification, however a continuous-time (CT) design offers significant advantage in the design of high accuracy, high speed analog to digital converters (ADC). A CT design allows for relaxed amplifier(s) bandwidth and power requirements, which enables the realization of high accuracy modulators with bandwidths of several megahertz at low power consumption. Furthermore CT modulators provide inherent anti-aliasing filtering which becomes especially important at low oversampling ratios. This thesis reports the design of a... 

    High-Speed Low-Power 10-bit Pipeline Analog to Digital Converter

    , M.Sc. Thesis Sharif University of Technology Hashemi, Mohsen (Author) ; Sharif Khani, Mohammad (Supervisor) ; Atarodi, Mojtaba (Supervisor)
    Abstract
    High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 40 M sample/s with a power consumption of 20mW for the input level of 1Vp-p and a 1V power supply in 0.13μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized analytically which leads to simple back-envelope formulas to... 

    Systematic Design of Low Power Flash ADC

    , Ph.D. Dissertation Sharif University of Technology Chahardori, Mohammad (Author) ; Sadughi, Sirus (Supervisor) ; Sharifkhani, Mohamad (Co-Advisor) ; Atarodi, Mojtaba (Co-Advisor)
    Abstract
    Considering the drastical increasing of greenhouse gases in the atmosphere, especially carbon dioxide, reduction of these gases seems necessary to combat global warming. Fossil fuel power plants are one of the main sources of CO2 emission. In this thesis, CO2 capture from a natural gas fired combined cycle power plant using different oxygen percent in air feed is studied. Aspen Plus was used to evaluate the effect of this capture technology on the plant efficiency and energetic parameters of the system. Aspen Hysys is used to simulate Amine absorption tower and Air Separation cryogenic tower. Since the oxygen production plant, CO2 capture and transport are cost and energy intensive, the cost... 

    Low-Power Reconfigurable Pipeline ADC for Multi-Standard Communication

    , M.Sc. Thesis Sharif University of Technology Esmaeelzadeh, Hani (Author) ; Sharifkhani, Mohammad (Supervisor) ; Shoaee, Omid (Co-Advisor)
    Abstract
    With the rapid development of wireless communication standards, the co-existence of multiple standards in a single chip becomes inevitable. It is also fueling interest in analog to digital converters (ADCs) that are reconfigurable over a wide range of bandwidths and resolutions with adaptive power consumption. Employing such ADCs rather than using multiple individually power-optimized ADCs results in a great reduction of silicon area. Hence, a reconfigurable ADC can reduce time to market, and save costs.
    This thesis addresses the challenges exists in conventional reconfigurable methods, and presents a novel reconfiguration methodology for changing resolution in pipeline ADCs. The... 

    Compensation and Calibration of ADCs

    , M.Sc. Thesis Sharif University of Technology Khanmohammad, Hesam (Author) ; Sharif Khani, Mohammad (Supervisor)
    Abstract
    Increasing demand for high-speed and high-resolution ADCs as much as low-power ones and on the other hand, the obstacles in the way of reaching them make calibration and compensation methods more significant for obtaining ADCs with the better specs. Among the cases which need modification, the modification of C-2C-based SAR ADCs, which can decrease the power significantly, and the modification of time-skew error of time-interleaved ADCs, which is the main and the most challenging error in this type of ADCs, could be the two of the effective ways to making the State-of-the-Art ADCs. In this project for the first time, a novel compensation method for C-2C parasitic charges is proposed which... 

    Design and Fabrication of Analog to Digital Converter for On­ Chip Measurement in Industrial Applications in 180nm­-HV BCD CMOS Proccess

    , M.Sc. Thesis Sharif University of Technology Ghaedi Bardeh, Mohammad (Author) ; Medi, Ali (Supervisor)
    Abstract
    Increasing demand for digital systems has led to developing signal processing in the digital domain. For this purpose, Analog to Digital Converters is used to convert analog signals to digital ones. Apart from that, by decreasing the size of transistors, it has been possible to implement the system on a chip that needs communication between analog and digital signals. The designed converter in this project is suitable for instrumentation purposes and especially for use in the control loop of a DC­DC digitally voltage converter. ADC architectures are mainly classified into two groups attributed with high bandwidth or with high resolution. Nature of on­chip measurement requires high... 

    SNR Improvement in A/D Converters Using Iterative Algorithm

    , M.Sc. Thesis Sharif University of Technology Kaffashan, Mohammad Mehdi (Author) ; Marvasti, Farrokh (Supervisor)
    Abstract
    Converting analog signal to digital one is one of the most important issues in signal processing which can be done by using analog to digital converter (A/D). In the first part of this thesis, sigma delta converters based on minimum support filter are investigated. Then, we will show that iterative algorithm can be used in order to improve the performance of the overall system significantly. Asynchronous converters can be utilized for the sake of decreasing power in the process of analog to digital converting. In these converters, a few numbers of samples will be taken from the regions which signal has high autocorrelation. In other words, samples in the asynchronous converters have more... 

    Design of a Low Power Monotonic SAR ADC with Offset Flattening

    , M.Sc. Thesis Sharif University of Technology Fateminia, Mohammad Javad (Author) ; Sharifkhani, Mohammad (Supervisor)
    Abstract
    The successive approximation digital to analog converters are appropriate selection for use in new technologies and low-powered applications. Despite the low power consumption of this kind of converters, there are some applications like medical which require very low power consumption. In order to reduce the power consumption of SAR ADC, capacitive digital to analog converters and comparators are great importance. In this Thesis, monotonic switching method has been used, the switching power of this method is lower than the conventional method by 81.2%. Since the common mode of the output of this type of switch is variable, the offset is sensitive and requires a technique to resolve this... 

    An Optimized Automated Design Algorithm for Pipeline ADC

    , M.Sc. Thesis Sharif University of Technology Sadrafshari, Mir Vala (Author) ; Sharifkhani, Mohammad (Supervisor)
    Abstract
    Analog to digital converters with different specifications are widely used in modern electronic circuits. The significant demand on pipeline converters in several low power applications is mainly due to their high speed and high resolution characteristics. Fast and simple design of analog circuits using CAD tools, is highly sought after by integrated circuit designers. In this thesis, pipeline analog to digital converters is studied and a CAD tool is proposed for transistor level design and optimizations. The main advantage of this design in comparison with the previous works is that the yield and power consumption are considered as optimization factors. The module operates in three parts:... 

    Two-level OOC-based fiber-optic CDMA systems with QoS using optical analog-digital converter (ADC)

    , Article 2009 Asia Communications and Photonics Conference and Exhibition, ACP 2009 ; 2-6 November , 2009 ; 21622701 (ISSN) ; 9781557528773 (ISBN) Ghaffari, B. M ; Salehi, J. A ; Sharif University of Technology
    Optical Society of America  2009
    Abstract
    A novel two-level signaling technique in OOC-based fiber-optic CDMA systems is proposed. The users of the system are categorized into two classes. Users of class 1 and 2 transmit the optical pulses at power level P and 2P respectively. At the receiver side using optical ADC multi-access interference is considerably suppressed. © 2009 OSA  

    Design and Implementation of Baseband Processing Algorithms in Massive MIMO Systems

    , M.Sc. Thesis Sharif University of Technology Mirfarshbafan, Hadi (Author) ; Shabany, Mahdi (Supervisor)
    Abstract
    Massive MIMO is a key enabling technology in the fifth generation (5G) wireless communication systems. In this technology, the base station is equipped with a large number of antennas (e.g. 100-200) and communicates with a relatively smaller number of user terminals. The large number of antennas at the base station, on one hand, has enabled unprecedented improvements in data rate and energy-efficiency, while on the other hand has posed challenges on the practical deployment of this technology.One of these challenges, is the high computational complexity of the baseband processing algorithms, such as precoding, due to the large number of antennas. In this research, we propose a novel ZF... 

    Applications and performance of optical analog-to-digital converter and optical logic gate elements in multilevel multiclass fiber-optic CDMA systems

    , Article IEEE Journal on Selected Topics in Quantum Electronics ; Volume 16, Issue 5 , 2010 , Pages 1476-1485 ; 1077260X (ISSN) Ghaffari, B. M ; Salehi, J. A ; Sharif University of Technology
    Abstract
    In this paper, we present and analyze a novel all-optical multilevel multiclass optical code division multiple access (OCDMA) system, using optical analog-to-digital converter (ADC) and advanced optical logic gate elements. In such OCDMA network, users are distributed in Mdifferent classes. Furthermore, power level with which users in class j,j = 2⋯M, transmit optical pulses, is twice the power level at which users of class j - 1transmit their optical pulses. We achieve optical transmitter structure that satisfies these conditions using power control schemes. Also, we suggest two receiver structures for the aforementioned multiclass multilevel system. The first and simple receiver structure... 

    Beamforming, null-steering, and simultaneous spatial and frequency domain filtering in integrated phased array systems

    , Article AEU - International Journal of Electronics and Communications ; Volume 110 , 2019 ; 14348411 (ISSN) Karami, P ; Atarodi, S. M ; Sharif University of Technology
    Elsevier GmbH  2019
    Abstract
    In the case that phased array systems are not capable of attenuating interferences, Radio Frequency (RF) front-ends and Analog Digital Converters (ADCs) with a large dynamic range are required to avoid saturation of the receiver. This leads to a higher power consumption. In this paper, employing N-path circuits in Mixer-First receivers, a novel method is introduced in which spatial and frequency blockers are eliminated right before entering the system on the antennas input. In fact using this technique, adjustable spatial notch filter and band-pass frequency filter are implemented to suppress spatial and frequency interferences. The proposed method enhances the robustness and effectiveness... 

    High Speed Digital Receiver, Design and Implementation

    , M.Sc. Thesis Sharif University of Technology Aarabi, Masoud (Author) ; Sanaei, Esmaeel (Supervisor) ; Pezeshk, Amir Mansoor (Supervisor)
    Abstract
    Nowadays, increasingly improvements in the digital technology and the advantages of using digital signal processing methods lead engineers to use digital signal processing instead of analog processing in variant domains. However, speed limitations in analog to digital converters (ADCs) and data transfer ports prevent its penetration to high frequency signals region. In this thesis, an Instantaneous Frequency Measurement (IFM) system that can measure frequency in the range of 2-18 GHz is implemented fully digital (DIFM) on FPGA. To do so, monobit sampling technique with the sampling rate of 10 GHz is selected, and GTX high speed serial port is configured to transfer digital data into FPGA.... 

    10-Bit 500-MS/s Pipelined Analog to Digital Converter

    , M.Sc. Thesis Sharif University of Technology Noormohammadi Khyarak, Mehdi (Author) ; Hajsadeghi, Khosrow (Supervisor)
    Abstract
    High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 500 M sample/s with a power consumption of 50mW for the input level of 1Vp-p and a 1.5V power supply in 0.18μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized .And to...