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Fully Digital Implementation and Optimization of Openhole Oil Well Surface Modem
, M.Sc. Thesis Sharif University of Technology ; Movahedian, Hamid (Supervisor) ; Gholampour, Iman (Co-Supervisor)
Abstract
Once a well has been drilled before it is cased with the steels (open-hole well), some logging must be done to record information’s about layers, geologic formations, geophysical and petrophysical properties of well. All the information’s that gathered from sensors and tools transmitted to the surface by a down-hole modem. This information is corrupted during the transmission by the communication channel. The most notable influence of this channel is noise, attenuation and interference between successive data bits. On the other hand, the characteristic of channel changes with the length of the cable, temperature, connections and so on. So using a set of fixed filters is not effective. The...
Clock and Data Recovery Circuit For High Speed Serial Communication
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosroo (Supervisor)
Abstract
In this thesis, A novel approach for ¼-rate clock Phase Detector (PD) structure for Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) is proposed. In this approach, the retimed data is generated within the circuit and no extra circuit is needed. Another advantage of this topology is that the error and reference signals are independent of delay time through gates and no extra replica circuit is needed to compensate the delay. This topology results in a lower power circuit and smaller area for high speed application compared to conventional topologies
Design and Fabrication of Analog to Digital Converter for On Chip Measurement in Industrial Applications in 180nm-HV BCD CMOS Proccess
,
M.Sc. Thesis
Sharif University of Technology
;
Medi, Ali
(Supervisor)
Abstract
Increasing demand for digital systems has led to developing signal processing in the digital domain. For this purpose, Analog to Digital Converters is used to convert analog signals to digital ones. Apart from that, by decreasing the size of transistors, it has been possible to implement the system on a chip that needs communication between analog and digital signals. The designed converter in this project is suitable for instrumentation purposes and especially for use in the control loop of a DCDC digitally voltage converter. ADC architectures are mainly classified into two groups attributed with high bandwidth or with high resolution. Nature of onchip measurement requires high...
Design and Analysis of Low-Power VLSI Clock Distribution Networks, Considering Process Variations
,
M.Sc. Thesis
Sharif University of Technology
;
Sarvari, Reza
(Supervisor)
Abstract
The Technology scaling and reduction of the size of transistors has led to an increase in the switching speed and, as a result, to an increase in the clock frequency.But in recent years, the continuation of this process of increasing the clock frequency has been almost stopped considering the considerations of power consumption. Previous research has shown that approximately 30-50% of the dynamic power consumed by the microprocessor is wasted in the clock distribution network.Therefore, the design of clock distribution networks is a big challenge for future microprocessors due to the trend of Technology scaling and process variation. In this thesis, we used the emerging technology of...
Low power Clock and Data Recovery Circuits in 20Gb/s Range in CMOS Technology
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
Growing demand for increased data transmission in communication systems and the internet, has intensified the need to increase the bandwidth of high speed transceivers. One of the main elements in high speed receivers is the clock and data recovery circuit which guarantees the transfer of data with high reliability. In this thesis, the design of a clock and data recovery circuit for high frequency applications is considered. The aim of this project is the design of a circuit with low power and low jitter for high-speed input data. A new four stage LC ring oscillator is designed that works at the quarter rate of the input. A new idea for the design of the binary phase detectors has also been...
Design of Clock and Data Recovery Circuits Inmulti Gb/s Range in CMOS Technology
, M.Sc. Thesis Sharif University of Technology ; HajSadeghi, Khosrow (Supervisor)
Abstract
Some applications need fast locking clock and data recovery circuits for example the circuits that operate in burst mode must lock to the data packets which are transmitting from different transmitters very quickly and in just a few bit times. In such applications open-loop clock and data recovery circuits are used because lock time in closed-loop clock and data recovery circuits is usually much longer.
In this thesis a new open loop clock and data recovery circuit based on injection locking method has been proposed. This circuit can be used in applications such as passive optical networks that need fast locking. In this architecture a super harmonic injection-locked frequency divider...
In this thesis a new open loop clock and data recovery circuit based on injection locking method has been proposed. This circuit can be used in applications such as passive optical networks that need fast locking. In this architecture a super harmonic injection-locked frequency divider...
Statistical Analysis of Optical Clock Recovery System Based on Second Harmonic Generation (SHG) Detection Scheme in Optical Networks
, M.Sc. Thesis Sharif University of Technology ; Salehi, Javad (Supervisor)
Abstract
In this thesis, we statistically model and analyze one of the main systems in optical communications which are based on Second HarmonicGeneration (SHG) process. To this end, we first introduce various applications of this process in optical communication systems and see that the main application of this nonlinear process is in the process of optical clock recovery in both of OTDM and SPE_OCDMA networks. In the rest of the thesis, we characterize the mathematical structure of these systems and use that to statistically analyze their behavior. In considering the optical clock recovery system based on SHG, we introduce three intrinsic sources of timing jitter in the system, namely, the On-Off...
A Survey on the Notion of Time in Quantum Mechanics from both Theoretical and Experimental Perspectives
, M.Sc. Thesis Sharif University of Technology ; Shafiee, Afshin (Supervisor)
Abstract
This project examines time in quantum mechanics, which includes three chapters. The first chapter is about clocks, which first deals with the history and invention of clocks, and then goes on to describe quantum clocks and various theories about them, including Perez and Faraday quantum clocks . The second chapter deals with the two-slit Yang experiments which, as in the preceding chapter, we first give a historical description of the experiment, and we will continue with our description. We consider that for each of these cases the probability of spatial and linear momentum interference is calculated. The third chapter is the final chapter. In this section, we first discuss the concept of...
All-Optical Clock Recovery Using Nonlinear Kerr Effect in Optical Fibers
, M.Sc. Thesis Sharif University of Technology ; Salehi, Javad (Supervisor)
Abstract
In this thesis, a brief review of the previously introduced all optical clock recovery methods are presented and then, two novel all optical PLLs, based on nonlinear Kerr effects in fiber optics, are introduced and thoroughly investigated. To obtain more insight into the subject, firstly, nonlinear Kerr effect and its two main applications, including FOPA amplifiers and optical Kerr shutters are described. One of the proposed PLLs employs a FOPA in its error signal detection process, and the other is based on using two Kerr shutter switches to detect the error signal. Since the PLLs are based on the quasi-instantaneous Kerr effect, they are expected to be suitable in ultra-high speed...
Clock and Data Recovery based on Phase Shifting and Accordion Oscillator
, M.Sc. Thesis Sharif University of Technology ; Fotowat Ahmady, Ali (Supervisor) ; Akbar, Fatemeh (Supervisor)
Abstract
The continuous growth of network traffic and people's demand for higher data rates, have driven wireline communication systems towards higher data rates. In these systems, the power consumption of these transmitters and receivers is a crucial and influential factor. This paper presents two different solutions to reduce the power consumption and area of these systems. In the first solution, a low-power phase shifter with variable phase and amplitude control is introduced. The changes in these parameters are mutually orthogonal, ensuring that a change in one characteristic does not affect the others. This phase shifter can be used to generate clock pulses with different phases in wireline...
VLSI implementation of a hardware-optimized lattice reduction algorithm for WiMAX/LTE MIMO detection
, Article ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 30 May 2010 through 2 June 2010, Paris ; 2010 , Pages 3541-3544 ; 9781424453085 (ISBN) ; Shabany, M ; Gulak, P. G ; Sharif University of Technology
2010
Abstract
This paper presents the first ASIC implementation of an LR algorithm which achieves ML diversity. The VLSI implementation is based on a novel hardware-optimized LLL algorithm that has 70% lower complexity than the traditional complex LLL algorithm. This reduction is achieved by replacing all the computationally intensive CLLL operations (multiplication, division and square root) with low-complexity additions and comparisons. The VLSI implementation uses a pipelined architecture that produces an LR-reduced matrix every 40 cycles, which is a 60% reduction compared to current implementations. The proposed design was synthesized in both 130μm and 65nm CMOS resulting in clock speeds of 332MHz and...
Value-Aware low-power register file architecture
, Article CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 44-49 ; 9781467314824 (ISBN) ; Fazeli, M ; Ghalaty, N. F ; Miremadi, S. G ; Sharif University of Technology
2012
Abstract
In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, "Value-Aware Partitioned Register File (VAP-RF)", employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure
Ultra high-throughput architectures for hard-output MIMO detectors in the complex domain
, Article Midwest Symposium on Circuits and Systems, 7 August 2011 through 10 August 2011l ; August , 2011 ; 15483746 (ISSN) ; 9781612848570 (ISBN) ; Shabany, M ; Sharif University of Technology
2011
Abstract
In this paper, a novel hard-output detection algorithm for the complex multiple-input multiple-output (MIMO) detectors is proposed, which results in a significant throughput enhancement, a near-ML performance, and an SNR-independent fixed-throughput. Moreover, a high-throughput VLSI implementation is proposed, which is based on a novel method of the node generation and sorting scheme. The proposed design achieves the throughput of 10Gbps in a 0.13 μ CMOS process, which is the highest throughput reported in the literature for both the real and the complex domains. Synthesis results in 90nm CMOS also show that the proposed scheme can achieve the throughput of up to 15Gbps. Moreover, the FPGA...
Top-down design of a low-power multi-channel 2.5-Gbit/s/channel gated oscillator clock-recovery circuit
, Article Design, Automation and Test in Europe, DATE '05, Munich, 7 March 2005 through 11 March 2005 ; Volume I , 2005 , Pages 258-263 ; 15301591 (ISSN); 0769522882 (ISBN); 9780769522883 (ISBN) ; Tajalli, A ; Atarodi, M ; Leblebici, Y ; Sharif University of Technology
2005
Abstract
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down to the transistor level, as well as to achieve a power consumption as low as 5mW/Gbit/s. Statistical simulation is used to estimate the achievable bit error rate in presence of phase and frequency errors and to prove the feasibility of the concept. VHDL modeling provides extensive verification of the topology. Thermal noise modeling based on well-known concepts delivers design parameters for the device sizing and biasing. We present two...
Theoretical considerations in designing ultra-high speed all-optical clock recovery using fiber optical parametric amplifiers
, Article Journal of Lightwave Technology ; Vol. 32, issue. 15 , August , 2014 , pp. 2678-2689 ; ISSN: 07338724 ; Salehi, J. A ; Sharif University of Technology
Abstract
In this paper, a new all-optical phase-locked loop (OPLL) in a TDM system is proposed and analyzed. The scheme relies on using fiber optical parametric amplifier (FOPA) device models and theories. In the proposed OPLL, the local clock pulse stream and the received data signal pulses are fed into the FOPA as its pump and amplified signals, respectively. The power of the resulting, relatively, strong idler signal depends on the phase difference between the local clock and the received data signal pulses, and it is used to reveal the OPLL's error signal. We characterize the mathematical structure of the proposed OPLL and identify its three intrinsic sources of phase noises namely, randomness of...
Systematic modeling and simulation of DLL-based frequency multiplier
, Article 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010, 4 October 2010 through 6 October 2010 ; 2010 ; 9781424468164 (ISBN) ; Sharifkhani, M ; Ebrahimi, A ; Saeedi, S ; Atarodi, M ; Sharif University of Technology
Abstract
This paper represents a systematic procedure of simulating charge pump based delay locked loops (DLLs). The presented procedure is based on the systematic modelling of the DLL components in Matlab simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented
Synchronizing hindmarsh-rose neurons over newman-watts networks
, Article Chaos ; Volume 19, Issue 3 , 2009 ; 10541500 (ISSN) ; Sharif University of Technology
American Institute of Physics Inc
2009
Abstract
In this paper, the synchronization behavior of the Hindmarsh-Rose neuron model over Newman-Watts networks is investigated. The uniform synchronizing coupling strength is determined through both numerically solving the network's differential equations and the master-stability-function method. As the average degree is increased, the gap between the global synchronizing coupling strength, i.e., the one obtained through the numerical analysis, and the strength necessary for the local stability of the synchronization manifold, i.e., the one obtained through the master-stability-function approach, increases. We also find that this gap is independent of network size, at least in a class of networks...
Switched-resistor: A new family of sampled-data circuits
, Article AEU - International Journal of Electronics and Communications ; Volume 63, Issue 5 , 2009 , Pages 366-373 ; 14348411 (ISSN) ; Bakhtiar, M. S ; Sharif University of Technology
2009
Abstract
This paper introduces "switched-resistor" circuits as a new family of current-mode sampled-data circuits with improved accuracy and linearity. Advantages of the switched-resistor circuits for high-speed and low-voltage applications are demonstrated. A switched-resistor biquad band-pass filter with a quality factor of 10 and clock frequency of 100 MHz, fabricated in a 0.18 μ m CMOS process, is also presented. The filter consumes 9 mW from 1.8 V supply. © 2008 Elsevier GmbH. All rights reserved
Seeking better times: Atomic clocks in the generalized Tonks-Girardeau regime
, Article Journal of Physics: Conference Series ; Volume 99, Issue 1 , 2008 ; 17426588 (ISSN) ; Del Campo, A ; Lizuain, I ; Pons, M ; Muga, J. G ; Sharif University of Technology
Institute of Physics Publishing
2008
Abstract
First we discuss briefly the importance of time and time keeping, explaining the basic functioning of clocks in general and of atomic clocks based on Ramsey interferometry in particular. The usefulness of cold atoms is discussed, as well as their limits if Bose-Einstein condensates are used. We study as an alternative a different cold-atom regime: the Tonks-Girardeau (TG) gas of tightly confined and strongly interacting bosons. The TG gas is reviewed and then generalized for two-level atoms. Finally, we explore the combination of Ramsey interferometry and TG gases. © 2008 IOP Publishing Ltd
Robust register caching: An energy-efficient circuit-level technique to combat soft errors in embedded processors
, Article IEEE Transactions on Device and Materials Reliability ; Volume 10, Issue 2 , February , 2010 , Pages 208-221 ; 15304388 (ISSN) ; Namazi, A ; Miremadi, S. G ; Sharif University of Technology
2010
Abstract
This paper presents a cost-efficient technique to jointly use circuit- and architecture-level techniques to protect an embedded processor's register file against soft errors. The basic idea behind the proposed technique is robust register caching (RRC), which creates a cache of the most vulnerable registers within the register file in a small and highly robust cache memory built from circuit-level single-event-upset-protected memory cells. To guarantee that the most vulnerable registers are always stored in the robust register cache, the average number of read operations during a register's lifetime is used as a metric to guide the cache replacement policy. A register is vulnerable to soft...