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Spectrum Sensing Algorithm and Implementation for Cognitive Radio Applications
, M.Sc. Thesis Sharif University of Technology ; Fotowat Ahmadi, Ali (Supervisor)
Abstract
The continous growth of wireless networks, the increasing numbers of users and devices, along with the demand for higher data rates have intensified the frequency band limitations as the communication medium. In search for more efficient methods to use this limited resource, the cognitive radio approach that allocates the local unused frequency bands to potential users has attracted considerable attension.
A fundamental and unseperable part of any cognitive radio system is its need to search, detect and understand the surrounding frequency spectrum. Although various methods have been already propose to overcome the challenges of this domain, simpler and more reliable methods are still in...
A fundamental and unseperable part of any cognitive radio system is its need to search, detect and understand the surrounding frequency spectrum. Although various methods have been already propose to overcome the challenges of this domain, simpler and more reliable methods are still in...
Design and Simulation of CMOS Based Magnetic Sensor for Biosensing Applications
, M.Sc. Thesis Sharif University of Technology ; Akbari, Mahmood (Supervisor) ; Fotowat-Ahmady, Ali (Supervisor)
Abstract
This paper presents a scalable and ultrasensitive magnetic biosensing scheme based on on-chip LC resonance frequency-shifting. The sensor transducer gain is demonstrated as being location-dependent on the sensing surface and proportional to the local polarization magnetic field strength |B|2 generated by the sensing inductor. To improve the gain uniformity, a periodic coil is proposed as a substitution for the standard process coil. As an implementation example, the circuit is designed in a 65nm CMOS process. The spatially uniform sensor gain of the array is verified by COMSOL simulations. Overall, the presented sensor demonstrates an improvement in the uniformity of the inductor’s magnetic...
Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - μm CMOS technology
, Article International Journal of Circuit Theory and Applications ; Volume 40, Issue 9 , MAR , 2012 , Pages 957-974 ; 00989886 (ISSN) ; Atarodi, S. M ; Luong, H. C ; Sharif University of Technology
Wiley
2012
Abstract
This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-μm technology. The chip area is 2.65 mm × 1.35 mm including...
Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology
, Article Turkish Journal of Electrical Engineering and Computer Sciences ; Volume 25, Issue 2 , 2017 , Pages 1035-1047 ; 13000632 (ISSN) ; Asgari, B ; Tabandeh, M ; Fazeli, M ; Sharif University of Technology
Turkiye Klinikleri Journal of Medical Sciences
2017
Abstract
In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75%...
A bridge technique for memristor state programming
, Article International Journal of Electronics ; Volume 107, Issue 6 , 2020 , Pages 1015-1030 ; Maymandi Nejad, M ; Haghzad Klidbary, S ; Bagheri Shouraki, S ; Sharif University of Technology
Taylor and Francis Ltd
2020
Abstract
In order to effectively use a memristor in analog circuits, its memristance should be adjusted to a desired value between its limits. Since the maximum and minimum required memristance typically varies considerably between different types of memristors, it is almost impossible to tune the resistance of each memristor based on a reference resistor. Which is mostly done using some programmer circuits. Moreover, those programming strategies involving pulses are time-consuming and they impose high hardware headroom. In this paper, a novel CMOS circuit is presented for programming memristors. A Wheatstone bridge circuit is used to measure the current memristance, while the programming current is...
Switch level fault emulation
, Article Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) ; Volume 2778 , 2003 , Pages 849-858 ; 03029743 (ISSN); 3540408223 (ISBN); 9783540408222 (ISBN) ; Ejlali, A ; Sharif University of Technology
Springer Verlag
2003
Abstract
The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch...
An efficient architecture for Sequential Monte Carlo receivers in wireless flat-fading channels
, Article Journal of Signal Processing Systems ; Volume 68, Issue 3 , 2012 , Pages 303-315 ; 19398018 (ISSN) ; Sharif University of Technology
Springer New York LLC
2012
Abstract
A pipelined architecture is developed for a Sequential Monte Carlo (SMC) receiver that performs joint channel estimation and data detection. The promising feature of the proposed SMC receiver is achieving the near-bound performance in fading channels without using any decision feedback, training or pilot symbols. The proposed architecture exploits the parallelism intrinsic to the algorithm and consists of three blocks, i.e., the SMC core, weight calculator, and resampler. Hardware efficient/parallel architectures for each functional block including the resampling block is developed. The novel feature of the proposed architecture is that makes the execution time of the resampling independent...
A comprehensive survey on UHF RFID rectifiers and investigating the effect of device threshold voltage on the rectifier performance
, Article Analog Integrated Circuits and Signal Processing ; Volume 96, Issue 1 , 2018 , Pages 21-38 ; 09251030 (ISSN) ; Sheikhaei, S ; Fotowat Ahmady, A ; Forouzandeh, B ; Sharif University of Technology
Springer New York LLC
2018
Abstract
Rectifiers are an integral part of power harvesting systems. In this paper, the literature on RF power rectifiers is surveyed, starting from the well-known voltage doubler. Effects of using low turn-on voltage devices on forward and reverse losses, and therefore, on conversion efficiency, is discussed. Samples of rectifiers with external devices, such as Schottky diodes are presented. Idea of external Vth cancellation through a rechargeable battery, self Vth cancellation, and floating gate transistors with charge injection onto the gates are demonstrated. Then, standard bridge rectifier and its modified versions, including Vth cancellation technique, are explained. Using low voltage devices...
Pipelining method for low-power and high-speed SAR ADC design
, Article Analog Integrated Circuits and Signal Processing ; Volume 87, Issue 3 , 2016 , Pages 353-368 ; 09251030 (ISSN) ; Saeedi, S ; Atarodi, M ; Sharif University of Technology
Springer New York LLC
Abstract
A low power analog to digital converter (ADC), based on a pipelining method employed in successive approximation register (SAR) architecture is presented. This structure is a two-stage pipeline SAR ADC with asymmetrical time interleaved (TI) channels, aimed to reach sampling rate as high as about threefold of a conventional SAR ADC while benefiting from its low power consumption and small area. Passive residue conversion without inter-stage amplifier and symphonic collaboration of stages are employed to design a low power, high speed, and accurate converter. In the proposed architecture, every signal sample experiences equal comparator offset during its conversion due to the applied novel...
CMOS integrated delay chain for X-Ku band applications
, Article Analog Integrated Circuits and Signal Processing ; Volume 102, Issue 1 , 2020 , Pages 213-224 ; Daryabari, F ; Medi, A ; Sharif University of Technology
Springer
2020
Abstract
A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 μ m CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from...
Low-power high-speed phase frequency detector based on carbon nano-tube field effect transistors
, Article Analog Integrated Circuits and Signal Processing ; 2021 ; 09251030 (ISSN) ; Sadughi, S ; Razaghian, F ; Sharif University of Technology
Springer
2021
Abstract
A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of...
An 8-bit current-mode folding ADC with optimized active averaging network
, Article Scientia Iranica ; Volume 15, Issue 2 , 2008 , Pages 151-159 ; 10263098 (ISSN) ; Sharif Bakhtiar, M ; Sharif University of Technology
Sharif University of Technology
2008
Abstract
In this paper, an 8-bit CMOS current-mode folding-interpolating ADC is presented. A new active averaging-interpolating network is described, which results in a better error correction factor compared to its resistive counterpart. Using novel circuits for fast settling and careful transistor sizing, a fast (>160 Msps) and low power (70 mW in 2.5 V supply voltage) 8-bit ADC, with a total chip area of 1 × 1.4 mm in a 0.25 micron CMOS process, is demonstrated. © Sharif University of Technology, April 2008
Optimum design of high power and high efficiency mm-wave fundamental oscillators
, Article International Journal of Circuit Theory and Applications ; Volume 46, Issue 8 , 2018 , Pages 1443-1461 ; 00989886 (ISSN) ; Kalantari, M ; Fotowat Ahmady, A ; Banai, A ; Sharif University of Technology
John Wiley and Sons Ltd
2018
Abstract
A systematic method to design high power and high efficiency mm-wave fundamental oscillators is presented. By using a linear time variant method, we first obtain the optimum conditions and show that these conditions can be significantly different for high power and high efficiency fundamental oscillation. Next, we propose a modified multistage ring oscillator with interstage passive networks to exploit the full capacity of the transistors in terms of output power or efficiency. Analytical expressions are also derived to determine the value of passive elements used in the oscillator. To verify the validity of the method, a 77-GHz two-stage (differential) VCO is designed in a 65-nm CMOS...
A new slew rate enhancement technique for operational transconductance amplifiers
, Article International Journal of Circuit Theory and Applications ; 2021 ; 00989886 (ISSN) ; Roozbakhsh, A ; Rasekhi, M ; Sharif University of Technology
John Wiley and Sons Ltd
2021
Abstract
This paper presents a new symmetric slew rate enhancement (SRE) circuit suitable for operational transconductance amplifiers (OTAs). The proposed SRE circuit is composed of two auxiliary circuits which are automatically activated during fast signal transitions (slewing) by comparing the input and output signals. The auxiliary circuits pump required current in/out the load capacitance. In this way, the slew rate of the amplifier is significantly improved without any extra static power dissipation. The proposed technique can be applied to a variety of operational amplifiers. However, incorporating the proposed SRE circuit into a folded-cascode amplifier (FCA) results in 7× slew rate...
A new slew rate enhancement technique for operational transconductance amplifiers
, Article International Journal of Circuit Theory and Applications ; Volume 50, Issue 3 , 2022 , Pages 997-1014 ; 00989886 (ISSN) ; Roozbakhsh, A ; Rasekhi, M ; Sharif University of Technology
John Wiley and Sons Ltd
2022
Abstract
This paper presents a new symmetric slew rate enhancement (SRE) circuit suitable for operational transconductance amplifiers (OTAs). The proposed SRE circuit is composed of two auxiliary circuits which are automatically activated during fast signal transitions (slewing) by comparing the input and output signals. The auxiliary circuits pump required current in/out the load capacitance. In this way, the slew rate of the amplifier is significantly improved without any extra static power dissipation. The proposed technique can be applied to a variety of operational amplifiers. However, incorporating the proposed SRE circuit into a folded-cascode amplifier (FCA) results in 7× slew rate...
A2CM2: Aging-aware cache memory management technique
, Article CSI Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2015, 7 October 2015 through 8 October 2015 ; October , 2015 , Page(s): 1 - 8 ; 9781467380478 (ISBN) ; Rohbani, N ; Farbeh, H ; Shirmohammadi, Z ; Miremadi, S. G ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most prone modules to NBTI. Variations in duty cycle and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and...
Design and Implementation of Time and Frequency Synchronization in LTE
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 23, Issue 12 , January , 2015 , Pages 2970-2982 ; 10638210 (ISSN) ; Shabany, M ; Nezamalhosseini, A ; Gulak, G ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
A novel architecture for efficient time and frequency synchronization, applied to the long-term evolution (LTE) standard, is proposed. For symbol timing, we propose applying a symbol-folding method on top of the sign-bit reduction technique, leading to a novel algorithm for the cyclic prefix-type recognition in LTE. Following the symbol timing, the fractional carrier frequency offset is estimated and compensated using an adaptive gain loop, which allows for a high-accuracy compensation in a short interval. In the frequency domain, for cell search, we propose a sign-bit reduction technique on top of the matched filter method for the primary synchronization signal detection. In addition, we...
A scalable dependability scheme for routing fabric of SRAM-based reconfigurable devices
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 23, Issue 9 , August , 2015 , Pages 1868-1878 ; 10638210 (ISSN) ; Asadi, H ; Khaleghi, B ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
With the continual scaling of feature size, system failure due to soft errors is getting more frequent in CMOS technology. Soft errors have particularly severe effects in static random-access memory (SRAM)-based reconfigurable devices (SRDs) since an error in SRD configuration bits can permanently change the functionality of the system. Since interconnect resources are the dominant contributor to the overall configuration memory upsets in SRD-based designs, the system failure rate can be significantly reduced by mitigating soft errors in routing fabric. This paper first presents a comprehensive analysis of SRD switch box susceptibility to short and open faults. Based on this analysis, we...
A high-throughput VLSI architecture for hard and soft SC-FDMA MIMO detectors
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 62, Issue 3 , January , 2015 , Pages 761-770 ; 15498328 (ISSN) ; Shabany, M ; Gulak, G ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) detector. Subsequently, it recognizes less reliable symbols for which more candidates in the constellation are browsed to improve the initial estimate. An efficient high-throughput VLSI architecture is also introduced achieving a superior performance compared to the conventional MMSE detectors with less than 28% added complexity. The performance of...
A novel area-efficient VLSI architecture for recursion computation in LTE turbo decoders
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 62, Issue 6 , 2015 , Pages 568-572 ; 15497747 (ISSN) ; Shabany, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
Long-term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next-generation wireless communication systems. Turbo codes, the specified channel-coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple maximum a posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are α and β recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing....