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Design and Fabrication of Buck-Boost DC-DC Converter and Linear Regulator With Digitally-Tunable Output Voltage in 0.18µm-HV BCD CMOS Process
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor)
Abstract
In this project, an inverting Buck-Boost converter with two negative linear regulator is designed, implemented and measured in CMOS 0.18μm-HV BCD technology. Input voltage of Buck-Boost converter can vary from +15V to +28 and output voltage is digitally adjustable from -1V to -10V. Maximum output current of the converter is 300mA. A current mode controller and a lag compensator is used to control the converter. A high speed highside current sensor is designed and used in current mode controller. Sampled current of the current sensor is also used in a current limit circuitary to limit the maximum current of highside switch. Two negative linear regulators are placed at the output of the...
Design and Implementation of Protected Smart High Side and Low Side Switch and Drivers in 0.18um HV BCD CMOS Technology
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Zolghadri, Mohammad Reza (Supervisor)
Abstract
In this thesis, two types of smart switch & driver chips are designed in 0.18 um HV BCD technology; low side driver and high side driver. These drivers are smart, because of having various types of protection and detection circuits, which protect switch, driver and connected load, versus errors that can be occurred by the user or other environmental effects. The protection circuits are battery over & under voltage shutdown, current limit, inductive load clamper and thermal shutdown. Load status is checked by status detection circuit and reported to user by one bit flag. Battery voltage can vary from 7 V to 40 V and output current is limited to 2 A. Designed high side and low side drivers are...
Design and Implementation of Local Interconnect Network (LIN)Transceiver in High Voltage BCD 0.18 um
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Faez, Ramin (Supervisor)
Abstract
In this study, a Local Interconnect Network (LIN) transceiver was designed and implemented. This chip contains transmitter, receiver, low power receiver, digital control unit, oscillator, voltage regulator, high voltage switch, temperature sensor and battery voltage detector. The main focus on this study was on designing transmitter,receiver, low power receiver and temperature sensor. Through designing of this chip, in addition to functional and physical layer specification that mentioned in ISO 17987, electromagnetic compatibility specifications have been considered significantly.The designed chip with slope control and wave shaping of BUS signal has excellent radiated emission performance....
Design of A Digitally Controlled Bias Chip For A Transceiver
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Sheikhaei, Samad (Supervisor)
Abstract
Advances in IC fabrication makes possible have systems on chips. In this thesis we have designed and fabricated a digitally controlled bias chip for a transceiver which can be programmed by its digital interface. In this thesis, briefly we review basics of voltage regulators and methods for controlling them. Then we introduce high voltage 0.18um CMOS technology. In this thesis, we describe the requirements of a specific transceiver and present a system to overcome these requirements. This system has positive, negative and internal regulators, a five-bit analog to digital converter, temperature sensors, power amplifier controller and digital serial interface. In this thesis, we present a...
A subthreshold symmetric SRAM cell with high read stability
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Vol. 61, issue. 1 , Jan , 2014 , p. 26-30 ; 15497747 ; Sharifkhani, M ; Hajsadeghi, K ; Sharif University of Technology
Abstract
This brief introduces a differential eight-transistor static random access memory (SRAM) cell for subthreshold SRAM applications. The symmetric topology offers a smaller area overhead compared with other symmetric cells for the same stability in the read operation. Two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability at the expense of read operation delay. Thorough postlayout Monte Carlo worst corner simulations in 45-nm CMOS technology are conducted. The proposed cell operates down to 0.35 V with a read noise margin of 74 mV and a write noise margin of 92 mV. Under this condition,...
12 bits, 40MS/s, low power pipelined SAR ADC
, Article Midwest Symposium on Circuits and Systems ; Aug , 2014 , p. 841-844 ; Hajsadeghi, K ; Sharif University of Technology
Abstract
This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
, Article Integration, the VLSI Journal ; Volume 46, Issue 4 , September , 2013 , Pages 413-426 ; 01679260 (ISSN) ; Manzuri Shalmani, M. T ; Sharif University of Technology
2013
Abstract
As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When...
A low-latency low-power QR-decomposition ASIC implementation in 0.13 μm CMOS
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 60, Issue 2 , 2013 , Pages 327-340 ; 15498328 (ISSN) ; Patel, D ; Gulak, P. G ; Sharif University of Technology
2013
Abstract
This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm 2 QRD chip,...
A VLSI architecture for multiple antenna eigenvalue-based spectrum sensing
, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, 9 December 2012 through 12 December 2012 ; December , 2012 , Pages 153-156 ; 9781467312615 (ISBN) ; Shabany, M ; Sharif University of Technology
2012
Abstract
An Eigenvalue-based detection (EBD) scheme, is proposed as an efficient method to overcome the noise uncertainty and the SNR wall problem in conventional energy detection (ED) schemes. Despite remarkable efforts made to analyze the EBD performance, a VLSI implementation is missing in literature. In this paper, a new FFT-based EBD algorithm is introduced, which eliminates the need for filter banks and discrete wavelet packet transform to channelize the input signal. The proposed method enables the utilization of the EBD algorithm in high-resolution spectrum sensing approaches. Moreover, it enables the detection of signals with SNRs as low as -10 dB. A low-power, area-efficient yet real-time...
A low complexity architecture for the cell search applied to the LTE systems
, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, 9 December 2012 through 12 December 2012 ; Dec , 2012 , Pages 300-303 ; 9781467312615 (ISBN) ; Sharifan, G ; Amini, Y ; Shabany, M ; Sharif University of Technology
2012
Abstract
Cell search is a crucial process in the synchronization procedure for the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) system. In this paper, a high-speed, low-complexity and reliable architecture is proposed for both steps of cell search: sector ID and cell ID group detection. For the sector ID detection, two novel methods, sign-bit reduction and wise resource sharing, are proposed. In addition, for the cell ID group detection, we proposed an algorithm based on the Maximum Likelihood Sequence Detection (MLSD) called 'sign-bit MLSD'. Simulations show that the proposed methods result in more than 90% reduction in area compared to the state-of-the-art. We designed and...
A 1-mW current reuse quadrature RF front-end for GPS L1 band in 0.18μm CMOS
, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, Seville, Seville, 9 December 2012 through 12 December 2012 ; 2012 , Pages 157-160 ; 9781467312615 (ISBN) ; Fotowat Ahmady, A ; Jenabi, M ; Sharif University of Technology
2012
Abstract
A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using...
A low power, eight-phase LC-ring oscillator for clock and data recovery application
, Article 2012 Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits, INMMIC 2012 ; 2012 ; 9781467329491 (ISBN) ; Hajsadeghi, K ; Sharif University of Technology
2012
Abstract
A four stage LC-ring oscillator is presented. Eight different phases are generated in which there in 45 degrees phase difference between consecutive outputs and direction of phases is defined. Nmos capacitors in parallel with constant capacitors are used for coupling between stages. The control voltage is applied to Pmos varactors to adjust the oscillation frequency. The advantages of this structure are the rather small inductors size, low power consumption, and tuning curve linearity. The proposed structure is simulated in 0.18um CMOS technology. Power consumption for each stage is 4.8mW from a 1.8B supply. The proposed VCO has a phase noise of -121dBc/Hz at 1MHz offset from the center...
Multi-level asynchronous delta-sigma modulation based ADC
, Article ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings, 12 June 2012 through 14 June 2012 ; Volume 2 , June , 2012 , Pages 725-728 ; 9781457719677 (ISBN) ; Aghdam, E. N ; Najafi, V ; Sharif University of Technology
2012
Abstract
A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous...
New operational transconductance amplifiers using current boosting
, Article Midwest Symposium on Circuits and Systems ; 2012 , Pages 109-112 ; 15483746 (ISSN) ; 9781467325264 (ISBN) ; Lazarjan, V. K ; HajSadeghi, K ; Sharif University of Technology
2012
Abstract
New techniques for Class-AB Operational Transconductance Amplifiers (OTAs) are presented. These new techniques are two topologies based on current boosting in class-AB stage which achieve considerable improvement of Slew Rate and Gain-Bandwidth while maintaining the same power consumption as the conventional design. Circuit level analysis and simulation results of proposed circuits in 0.18μm CMOS technology for gain, GBW, slew rate, and settling time are presented to prove the effectiveness of the proposed design method
Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - μm CMOS technology
, Article International Journal of Circuit Theory and Applications ; Volume 40, Issue 9 , MAR , 2012 , Pages 957-974 ; 00989886 (ISSN) ; Atarodi, S. M ; Luong, H. C ; Sharif University of Technology
Wiley
2012
Abstract
This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-μm technology. The chip area is 2.65 mm × 1.35 mm including...
Down-conversion self-oscillating mixer by using CMOS technology
, Article Proceedings - 2012 IEEE 8th International Colloquium on Signal Processing and Its Applications, CSPA 2012 ; 2012 , Pages 33-36 ; 9781467309615 (ISBN) ; Zahedi, A ; Sabaghi, M ; Ameri, S. R. H ; Niyakan, M ; Sharif University of Technology
2012
Abstract
In this paper a self-oscillating mixer is presented fundamental signal generated by the oscillator subcircuit in the mixing process. The oscillator core consumes 3mA of current from a 1.8 V DC supply and results in an output power of -0.867 dBm per oscillator, and a measured phase noise of -91, -102 and -108 dBc/Hz at 100 KHz, 600 KHz and 1 MHz from the carrier, respectively. In the mixing process the proposed mixer achieved IIP3 of 0 dBm with conversation gain of 1.93 dB. The circuit was designed and simulated in 0.18-μm CMOS technology by ADS2010
A full 360° vector-sum phase shifter with very low rms phase error over a wide bandwidth
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 60, Issue 6 PART 1 , 2012 , Pages 1626-1634 ; 00189480 (ISSN) ; Atarodi, M ; Sharif University of Technology
2012
Abstract
An innovative vector-sum phase shifter with a full 360° variable phase-shift range in 0.18-μm CMOS technology is proposed and experimentally demonstrated in this paper. It employs an I/Q network with high I/Q accuracy over a wide bandwidth to generate two quadrature basis vector differential signals. The fabricated chip operates in the 2.3-4.8 GHz range. The root-mean-square gain error and phase error are less than 1.1 dB and 1.4° over the measured frequency span, respectively. The total current consumption is 10.6 mA (phase shifter core: ∼2.6 mA) from a 1.8 V supply voltage and overall chip size is 0.87 × 0.75 mm 2. To the best of the authors' knowledge, this circuit is the first...
A method for noise reduction in active-rc circuits
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 58, Issue 12 , 2011 , Pages 906-910 ; 15497747 (ISSN) ; Bakhtiar, M. S ; Sharif University of Technology
Abstract
A method for noise reduction in active-$RC$ circuits is introduced. It is shown that the output noise in an active-$RC$ circuit can be considerably reduced, without disturbing the circuit transfer function by inserting appropriate passive or active components in the circuit. The inserted components introduce new signal paths in the circuit for noise reduction while the original circuit transfer function is kept unchanged. The procedure to define the proper paths in the circuit and their transfer functions is given. The effectiveness of the presented method is demonstrated using a second-order active-RC filter fabricated in a 0.18-$ {m}$ CMOS technology
A low-power current reuse CMOS RF front-end for GPS applications
, Article 2011 IEEE International RF and Microwave Conference, RFM 2011 - Proceedings, 12 December 2011 through 14 December 2011, Seremban ; 2011 , Pages 416-419 ; 9781457716294 (ISBN) ; Fotowat Ahmady, A ; Sharif University of Technology
Abstract
A very low-power RF front-end based on a new current reuse QLMV cell (Quadrature VCO-LNA-Mixer) is proposed for GPS applications. The front-end, designed in 0.18μm CMOS technology, provides improved performance characteristics while consuming only 1 mA current. Simulation results are presented and compared with recently published works in the field
Single event upset immune latch circuit design using C-element
, Article Proceedings of International Conference on ASIC, 25 October 2011 through 28 October 2011, Xiamen ; 2011 , Pages 252-255 ; 21627541 (ISSN) ; 9781612841908 (ISBN) ; Tabandeh, M ; Sharif University of Technology
2011
Abstract
Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in...