Sharif Digital Repository

In this paper, we present a very fast and accurate technique to estimate the soft error rate of digital circuits in the presence of Multiple Event Transients (METs). In the proposed technique, called Multiple Event Probability Propagation (MEPP), a four-value logic and probability set are used to accurately propagate the effects of multiple erroneous values (transients) due to METs to the outputs and obtain soft error rate. MEPP considers a unified treatment of all three masking mechanisms i.e., logical, electrical, and timing, while propagating the transient glitches. Experimental results through comparisons with statistical fault injection confirm accuracy (only 2.5% difference) and... 

Recently announcement of a physical realization of a fundamental circuit element called memristor by researchers at Hewlett Packard (HP) has attracted so much interest worldwide. Combination of this newly found element with crossbar interconnect technology, opened a new field in designing configurable or programmable electronic systems which can have applications in signal processing and artificial intelligence. In this paper, based on the simple memristor crossbar structure, we will propose a new mixed analog-digital circuit as a hardware implementation of the sign-sign least mean square (LMS) adaptive filter algorithm. In this proposed hardware, any multiplication and addition is performed... 

A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply  

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

In parallel with enhancements in the technology of integrated circuits, transistors are implemented in silicon. Though the price is reduced; design is more complicated, which create the efficiency and power consumption. The reason why modern GDI-based circuit is the focus of attention is that in designing digital circuit, less power is required while more efficiency is obtained. Lowering the complexity of logic circuit can bring about reduction of power consumption, propagation delay and decrease circuit space. GDI-based integrated circuit resembles MOSFET transistors but have fewer transistors and higher performance capability. This study addresses two main areas which are Studying and... 

In recent years, hardware Trojans (HTs) have become one of the main challenging concerns within the chain of manufacturing digital integrated circuit chips. Because of their diversity in chips, HTs are difficult to detect and locate. This paper attempted to propose a new improved method for detection and localization of HTs based on the real-time logical values of nodes. The algorithm extracts the nodes with special attributes. At the next stage, the nodes with the greatest similarity in terms of logical value are selected as targets. Depending on the size of the circuit, the extraction continues until a sufficient number of similar nodes has been selected. The logical relationship between... 

In this paper, we propose a mm-wave transmitter architecture intended for radar and 5G MIMO applications with beam steering over 57-63 GHz frequency band. Each transmitter chain comprises an all-digital phase-locked loop (ADPLL) CMOS IC chip intended to be dictated to a single antenna unit within an array. For demonstration purposes, each IC is embedded on a printed circuit board (PCB) to provide beam steering using highly accurate digital approach. The overall transmitter is connected to an antenna array with half wavelength spaced elements to maximize the beam scanning coverage. The ADPLL boards are fabricated and a calibration technique is carried out to align amplitude-phase of all... 

Hardware Trojans are one of the serious threats with detrimental, irreparable effects on the functionality, security, and performance of digital integrated circuits. It is difficult to detect Trojans because of their diversity in size and performance. While the majority of current methods focus on Trojan detection during chip testing, run-time techniques can be employed to gain unique advantages. This paper proposes a method based on the online scalable detection technique, which eliminates the need for a reference chip. Involving local detectors, this technique assesses the variations in the logical values of each node to find out whether there are Trojans. This method excludes time and... 

Microrings can have different hysteresis characteristics at their different resonance frequencies. They can be used as a multi-hysteresis optical component. In this paper an optical D-flip-flop circuit composed of a single nonlinear passive microring coupled to two straight waveguide based on the Kerr effect is proposed. The proposed circuit can operate as an optical digital circuit which synchronizes input DATA with the CLOCK of the circuit. A simple analytical model for hysteresis design and the transient analysis of the proposed D-flip-flop are presented. According to our model, the switching time of the flip-flop is in the order of 10 ps. Crown Copyright © 2008  

Datapath designs that perform polynomial computations over Z 2n are used in many applications such as computer graphics and digital signal processing domains. As the market of such applications continues to grow, improvements in high-level synthesis and optimization techniques for multivariate polynomials have become really challenging. This paper presents an efficient algorithm for optimizing the implementation of a multivariate polynomial over Z2n in terms of the number of multipliers and adders. This approach makes use of promising heuristics to extract more complex common sub-expressions from the polynomial compared to the conventional methods. The proposed algorithm also utilizes a... 

A CMOS fully differential UHF variable gain amplifier for use in a direct-conversion DVB-H receiver is presented employing input devices with variable aspect ratios. High linearity is achieved by reducing the transconductance of the input transistors for lower gain settings. It is shown that this technique has better linearity and noise performance compared to the conventional methods in which the gain reduction is performed at preceding stages. Implemented in TSMC 0.18-μm CMOS process, the inductorless RF VGA covers a voltage gain ranging from 15.5 dB to -6.5 dB with a maximum IIP3 of +24 dBm. The amplifier achieves a 3-dB bandwidth of 1.4 GHz and a minimum noise figure of 5.8 dB while... 

Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the... 

Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt. © 2008 IEEE  

Cartesian Genetic Programming (CGP) has an unusual genotype representation which makes it more efficient than Genetic programming (GP) in digital circuit design problem. However, to the best of our knowledge, all methods used in evolutionary design of digital circuits deal with rugged, complex search space, which results in long running time to obtain successful evolution. Therefore, employing a method to guide evolution in these spaces can facilitate achieving more reasonable results. It has been claimed that a two-step evolutionary scenario caused by benefit and cost of learning called Baldwin effect can guide evolution in the biology and artificial life. Therefore, we have been motivated... 

A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power... 

A new level converter for use in dual voltage SOI digital circuits is presented. The technique which uses the idea of keeper transistors, consumes less power compared to the traditional methods. The effects of load capacitance on the circuit are studied by extensive simulations  

In search of low cost and flexible substrates organic transistors have been suggested as an alternate to silicon transistors. Level 1 model extraction, investigating different circuit styles and proposing two new circuit styles for organic integrated circuits is done in this paper. First, level 1 model of organic transistor is found using ID-VDS characteristics of transistors reported by [9]. After that different design styles used in CMOS digital integrated circuits are reviewed and the functionality of these styles for organic integrated circuits is investigated. Two new circuit styles have been proposed in this section which have better performance for organic circuits comparing with... 

An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called 'Slew Boost' is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10 bit 150 MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp, using 0.18 μm CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than I mW from a single supply of I volt. © 2003 ACM