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digital-to-analog
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Circuit and Systematic Design of Low Power SAR ADC
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor)
Abstract
Low power and high speed analog-to-digital converters (ADCs) are the key elements of communication and computing systems. There are several ADC structures such as delta-sigma, flash, pipeline, and successive approximation register (SAR) for different applications, albeit SAR ADCs are natural candidates of onchip designs for their low power and scalability benefits. Nowadays, SAR ADCs are widely being used in low-power moderate-resolution applications which need several tens of MS/s to low GS/s sampling rates. By virtue of the technology scaling power consumption of digital parts of a SAR ADC is reduced significantly. As a result, in a SAR ADC the power consumption of the digital-to-analog...
Joint Source Channel Coding with Hybrid Digital Analog Codes in the Presence of Intereference
,
M.Sc. Thesis
Sharif University of Technology
;
Behroozi, Hamid
(Supervisor)
Abstract
In this thesis we consider transmitting an analog Gaussian source over an AWGN channel in the presence of an interference completely known at the transmitter intwo cases: 1) Compression bandwidth with interference uncorrelated with the sourceand 2) Matched bandwidth channel in the presence of interference correlated withthe source to be transmitted. We study joint source-channel coding schemes basedon hybrid digital-analog (HDA) codes. After providng a brief review, we will proposetwo new schemes for the ?rst case and one novel scheme for the second case. Aswe will see both schemes for the ?rst case achieve the optimal mean-squared error(MSE) distortion. The proposed HDA schemes can...
Analysis of C-2C DAC Mismatch Effects in SAR ADCs
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor)
Abstract
Analog to digital converters is one of the main building blocks of today's circuits. These circuits play an important role in signal processing. Since these circuits consist of analog and digital sections, a large percentage of the power consumed in a circuit is allocated to this section. Therefore, in applications such as medical devices, wearable applications and wireless technology where power control is very important and necessary, reducing the power of analog to digital converters is very important. One of the simplest analog-to-digital converters from the design point of view is Successive Approximation Register (SAR) analog-to-digital converters. This type of analog-to-digital...
Circuit & Systematic Design of Low Power & High Speed SAR ADC
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
SAR ADC is a data converter which is based on binary search to convert an analog signal to a digital signal. Unlike other converters like pipeline, most of its constituent parts are digital, and hence scalable with process and consume less power, moreover can have better speed and power performance. With advanced technologies, namely 45nm and 32 nm CMOS, SAR ADCs are preferable as they consume much less power and area, therefore well-suited for portable applications, as opposed to Flash and Pipleline converters.
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a...
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a...
Efficient Circuit and Systematic Design of Successive Approximation Register Analog to Digital Converters
, Ph.D. Dissertation Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
Successive Approximation Register (SAR) Analog to Digital Converter (ADC) converts an analog signal to a digital code based on binary search. In contrast to other converters, such as Pipeline and Flash ADCs, most of the SAR ADC components are digital, hence, SAR ADC is technology scalable. Therefore, designed using smaller tehcnologies, SAR ADCs are able to operate at a higher frequency with a lower power consumption and area. The main focus of this thesis is to reduce power consumption, although the proposed techniques and circuits are able to improve other features such as precision, area, or speed.Considering Digital to Analog Converter (DAC), a low-power structure and a novel method to...
Design of a Non-Bianry Analog to Digital Converterfor Impantable Neural Recording Microsystem
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor) ; Sodagar, Amir Masoud (Supervisor)
Abstract
A new structure of implantable neural recording microsystem base on multiple valued logic (MVL) has been proposed. MVL is a new idea for reduction of occupied area and the power consumption of microelectronic. In another side, in implantable microsystems , occupied area and power consumption by this type of micro systems is a challenging problem in this field. Therefore, the problem of power consumption and occupied area can introduce as a prime stage of suggested microsystem completed design of convertor of analog to digital in usage of multiple level in this micro system worked. Design of convertor of analog to digital is a convertor of quaternary successive approximation. And also,...
Design and implementation of a stable platform digital controller based on DSP
, Article ICSES 2008 International Conference on Signals and Electronic Systems, ICSES'08, Krakow, 14 September 2008 through 17 September 2008 ; 2008 , Pages 453-456 ; 9788388309526 (ISBN) ; Chamani Takaldani, H. R ; Moosavienia, A ; Monfaredi, K ; Ebrahimi Atani, R ; Sharif University of Technology
2008
Abstract
The principle, configuration, and the special features of a stable platform digital controller are presented in this paper. The main goal of this paper is replacing an analog controller with its awaiting digital one. This has been done using TMS320LF2402 digital signal processor which offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. The experimental results show that the digital controller is identical to the analog one and can be a suitable replacement for the analog controller. Copyright © 2008 by Department of Electronics, AGH University of Science and Technology
An accurate low-power DAC for SAR ADCs
, Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2017
Abstract
A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©...
Optimal HDA schemes for transmission of a Gaussian source over a Gaussian channel with bandwidth compression in the presence of an interference
, Article IEEE Transactions on Signal Processing ; Volume 60, Issue 4 , January , 2012 , Pages 2081-2085 ; 1053587X (ISSN) ; Behroozi, H ; Sharif University of Technology
2012
Abstract
We consider transmission of a Gaussian source over a Gaussian channel under bandwidth compression in the presence of an interference known only to the transmitter. We study hybrid digital-analog (HDA) joint source-channel coding schemes and propose two novel layered coding schemes that achieve the optimal mean-squared error (MSE) distortion. This can be viewed as the extension of results by Wilson ["Joint Source Channel Coding With Side Information Using Hybrid Digital Analog Codes," IEEE Trans. Inf. Theory, vol. 56, no. 10, pp. 4922-2940, Oct. 2010], originally proposed for sending a Gaussian source over a Gaussian channel in two cases: 1) Matched bandwidth with known interference only at...
Optimal HDA codes for sending a Gaussian source over a Gaussian channel with bandwidth compression in the presence of an interference
, Article 2011 IEEE Information Theory Workshop, ITW 2011 ; 2011 , Pages 325-329 ; 9781457704376 (ISBN) ; Behroozi, H ; Sharif University of Technology
2011
Abstract
In this paper, we consider transmission of a Gaussian source over a Gaussian channel under bandwidth compression in the presence of interference known only to the transmitter. We study hybrid digital-analog (HDA) joint source-channel coding schemes and propose two novel coding schemes that achieve the optimal mean-squared error (MSE) distortion. This can be viewed as the extension of results by Wilson et al. [1], originally proposed for sending a Gaussian source over a Gaussian channel in two cases: 1) Matched bandwidth with known interference only at the transmitter, 2) bandwidth compression where there is no interference in the channel. The proposed HDA codes can cancel the interference of...
A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects
, Article Integration ; Volume 69 , 2019 , Pages 321-334 ; 01679260 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier B.V
2019
Abstract
This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is...
A low voltage 14-bit self-calibrated CMOS DAC with enhanced dynamic linearity
, Article Analog Integrated Circuits and Signal Processing ; Volume 43, Issue 2 , 2005 , Pages 137-145 ; 09251030 (ISSN) ; Mehrmanesh, S ; Atarodi, M ; Sharif University of Technology
2005
Abstract
A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a...
A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity
, Article 2004 IEEE International Symposium on Circuits and Systems - Proceedings, Vancouver, BC, 23 May 2004 through 26 May 2004 ; Volume 1 , 2004 , Pages I349-I352 ; 02714310 (ISSN) ; Mehrmanesh, S ; Atarodi, M ; Aslanzadeh, H. A ; Sharif University of Technology
2004
Abstract
A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a novel background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a new low power track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding, to 14-bit specification are less than 0.35LSB and 0.25LSB, respectively. The DAC is functional up to 400MS/S with SFDR better than 71dB in the Nyquist band. The circuit has been...
A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application
, Article IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016-March , 2016 , Pages 153-156 ; 9781509002467 (ISBN) ; Khorami, A ; Eslampanah Sendi, M. S ; Hajsadeghi, K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively
A compact low power mixed-signal equalizer for gigabit ethernet applications
, Article ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 21 May 2006 through 24 May 2006 ; 2006 , Pages 5167-5170 ; 02714310 (ISSN); 0780393902 (ISBN); 9780780393905 (ISBN) ; Eghbalkhah, B ; Saeedi, S ; Afzali Kusha, A ; Atarodi, M ; Sharif University of Technology
2006
Abstract
In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter's coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 um CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply. © 2006 IEEE
Elimination of the effect of bottom-plate capacitors in C-2C DAC using a layout technique
, Article Microelectronics Journal ; Volume 46, Issue 12 , 2015 , Pages 1275-1282 ; 00262692 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Abstract
An efficient layout technique is proposed to eliminate the effect of the bottom-plate capacitors in a C-2C Digital to Analog Converter (DAC). Using this technique, the bottom-plate capacitors of 2C capacitors in the C-2C structure are placed in parallel with 1C capacitors. Then, the effect of the bottom plate capacitors is nulled by modifying the size of the main 1C capacitors. Hence, avoiding the complexity of calibration, this technique can preclude the effect of the bottom-plate to ground capacitance. Statistical simulations prove that the proposed technique is robust to non-ideal effects such as mismatch or parasitic capacitors. A 10-bit C-2C DAC is modeled in COMSOL Multiphysics using...
Zero-power mismatch-independent Digital to Analog converter
, Article Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, 7 June 2015 through 10 June 2015 ; June , 2015 , Page(s): - 4 ; 9781479988938 (ISBN) ; Sendi, M. S. E ; Nikoofard, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply
Zero-power mismatch-independent digital to analog converter
, Article AEU - International Journal of Electronics and Communications ; Volume 69, Issue 11 , 2015 , Pages 1599-1605 ; 14348411 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH
2015
Abstract
A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method
An ultra low-power DAC with fixed output common mode voltage
, Article AEU - International Journal of Electronics and Communications ; Volume 96 , 2018 , Pages 279-293 ; 14348411 (ISSN) ; Saeidi, R ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH
2018
Abstract
A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes....
An ultra low-power digital to analog converter for SAR ADCs
, Article Proceedings of the International Conference on Microelectronics, ICM, 10 December 2017 through 13 December 2017 ; Volume 2017-December , 2018 , Pages 1-4 ; 9781538640494 (ISBN) ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC. © 2017 IEEE