Search for: digital-to-analog-conversion
Article Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, 7 June 2015 through 10 June 2015 ; June , 2015 , Page(s): - 4 ; 9781479988938 (ISBN) ; Sendi, M. S. E ; Nikoofard, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2015
A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply
Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2017
A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©...
Article Proceedings of the International Conference on Microelectronics, ICM, 10 December 2017 through 13 December 2017 ; Volume 2017-December , 2018 , Pages 1-4 ; 9781538640494 (ISBN) ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2018
A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC. © 2017 IEEE
Article 27th Iranian Conference on Electrical Engineering, ICEE 2019, 30 April 2019 through 2 May 2019 ; 2019 , Pages 82-86 ; 9781728115085 (ISBN) ; Fakharzadeh, M ; Safarian, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2019
In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively
Article IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016-March , 2016 , Pages 153-156 ; 9781509002467 (ISBN) ; Khorami, A ; Eslampanah Sendi, M. S ; Hajsadeghi, K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively
Article Microelectronics Journal ; Volume 90 , 2019 , Pages 48-57 ; 00262692 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier Ltd 2019
A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The...
Article AEU - International Journal of Electronics and Communications ; Volume 69, Issue 11 , 2015 , Pages 1599-1605 ; 14348411 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH 2015
A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method
Article AEU - International Journal of Electronics and Communications ; Volume 96 , 2018 , Pages 279-293 ; 14348411 (ISSN) ; Saeidi, R ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH 2018
A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes....
A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects, Article Integration ; Volume 69 , 2019 , Pages 321-334 ; 01679260 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier B.V 2019
This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is...
Article ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings, 12 June 2012 through 14 June 2012 ; Volume 2 , June , 2012 , Pages 725-728 ; 9781457719677 (ISBN) ; Aghdam, E. N ; Najafi, V ; Sharif University of Technology
A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous...
Article Microelectronics Journal ; Volume 46, Issue 12 , 2015 , Pages 1275-1282 ; 00262692 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
An efficient layout technique is proposed to eliminate the effect of the bottom-plate capacitors in a C-2C Digital to Analog Converter (DAC). Using this technique, the bottom-plate capacitors of 2C capacitors in the C-2C structure are placed in parallel with 1C capacitors. Then, the effect of the bottom plate capacitors is nulled by modifying the size of the main 1C capacitors. Hence, avoiding the complexity of calibration, this technique can preclude the effect of the bottom-plate to ground capacitance. Statistical simulations prove that the proposed technique is robust to non-ideal effects such as mismatch or parasitic capacitors. A 10-bit C-2C DAC is modeled in COMSOL Multiphysics using...
Article ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, 23 August 2009 through 27 August 2009 ; 2009 , Pages 898-901 ; 9781424438969 (ISBN) ; Atarodi, M ; Sharif University of Technology
Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise
Article ICSES 2008 International Conference on Signals and Electronic Systems, ICSES'08, Krakow, 14 September 2008 through 17 September 2008 ; 2008 , Pages 453-456 ; 9788388309526 (ISBN) ; Chamani Takaldani, H. R ; Moosavienia, A ; Monfaredi, K ; Ebrahimi Atani, R ; Sharif University of Technology
The principle, configuration, and the special features of a stable platform digital controller are presented in this paper. The main goal of this paper is replacing an analog controller with its awaiting digital one. This has been done using TMS320LF2402 digital signal processor which offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. The experimental results show that the digital controller is identical to the analog one and can be a suitable replacement for the analog controller. Copyright © 2008 by Department of Electronics, AGH University of Science and Technology
Article 2007 IEEE Region 10 Conference, TENCON 2007, Taipei, 30 October 2007 through 2 November 2007 ; 2007 ; 1424412722 (ISBN); 9781424412723 (ISBN) ; Mehrmanesh, S ; Zamanlooy, B ; Atarodi, M ; Sharif University of Technology
A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power...
Article ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 21 May 2006 through 24 May 2006 ; 2006 , Pages 5167-5170 ; 02714310 (ISSN); 0780393902 (ISBN); 9780780393905 (ISBN) ; Eghbalkhah, B ; Saeedi, S ; Afzali Kusha, A ; Atarodi, M ; Sharif University of Technology
In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter's coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 um CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply. © 2006 IEEE